Wallace Tree Research Articles

Delineation of Optimized Single and Multichannel Approximate DA-Based Filter Design Using Influential Single MAC Strategy for Trans-Multiplexer.

In this paper, a multichannel FIR filter design based on the Time Division Multiplex (TDM) approach that incorporates one multiply and add unit, regardless of the variable coefficient length and varying channels, by associating the resource sharing doctrine is suggested. A multiplier based on approximate distributed arithmetic (DA) circuits is employed for effective resource optimization. Although no explicit multiplication was conducted in this realization, the radix-8 and radix-4 Booth algorithms are utilized in the DA framework to curtail and optimize the partial products (PPs). Furthermore, the input stream is truncated with an erratum mending unit to roughly construct the partial products. For an aggregation of PPs, an approximate Wallace tree is taken into consideration to further minimize hardware expenses. Consequently, the suggested design's latency, utilized area, and power usage are largely reduced. The Xilinx Vertex device is expedited, given the synthesis of the suggested multichannel realization with 16 taps, which is simulated using the Verilog formulary. It is observed that the filter structure with one channel produced the desired results, and the system's frequency can support up to 429 MHz with a reduced area. Utilizing TSMC 180 nm CMOS technology and the Cadence RC compiler, cell-level performance is also achieved.

Energy efficient Wallace multiplier using symmetric stacking counter circuit

Multipliers show a dynamic part in numerous uses such as digital signal processing, filters and so on. Hence, the performance of the multiplier circuit has also to be improved more for better results. The circuit of the multiplier should be more compact and efficient to achieve the best outcome. Symmetric stacking counter circuit is designed using reversible logic gates and it reduces the power consumption. Various symmetric stacked counters are designed and used to implement the Wallace tree multiplier. The proposed multiplier is consumes 0.798mw of power and PDP of 2.47. The designed multiplier is power efficient as compared with existing methods with slight increase in delay. The proposed multiplier is used in low power application like modulators and demodulators.

Energy-Efficient Approximate Multiplier with Flexible Precision

Abstract: The method that can be utilized to increase accuracy and decrease energy use is approximate multiplication. A key component of many error-tolerant applications is multiplication. Approximate multipliers are increasingly utilized in energyefficient computing for applications tolerant of inaccuracy. Apart from multiplier performance, determining the appropriate approximate multiplier is challenging due to considerations of area and delay. Therefore, selecting the type of approximate full adder (FA) becomes a crucial decision-making factor. These adders are employed for summing partial products in multipliers. This study presents the design and evaluation of an approximate multiplier employing four distinct approximate adders. The design undergoes simulation and synthesis using Xilinx and Model Sim. Compared to previously proposed approximate multipliers, the proposed circuits demonstrate substantial reductions in area, time delay, and power consumption. According to experimental data, the area, latency, and average power consumption of the suggested adjustable approximate multiplier can be lowered by 10%, 34.96 ns, and 300 mW when contrasted to the Wallace tree multiplier.

Design Wallace Tree Multiplier Using Reversible Gates

Abstract: Multipliers are essential components in digital circuit design. They have wide spread applications in digital signal processing and communication systems. Circuit designers in VLSI design seek compact, small scale circuits with low power consumption and minimal delay. The Wallace tree multiplier is an advanced version of tree based multipliers. Numerous algorithms have been developed to create the fastest multipliers, and the Wallace tree multiplier is one such example. It utilizes reversible compressors, full adders, and half adders. The results demonstrate that the Wallace tree multiplier using reversible gates outperforms traditional multipliers in terms of power dissipation and delay, with values of 0.027W and 29.327nS re­spectively.

Implementation of Digital Filter Using Verilog HDL

Abstract: In the context of Very Large Scale Integration technology, where addition is essential, digital filters are essential elements. The performance of the Finite Impulse Response Filter is highly dependent on the speed of its multiplier unit, making itstand out among the others. In order to improve the effectiveness of the FIR filter, we suggest using a Wallace tree multiplier. This novel method offers improvements over conventional multipliers, with a decrease in latency being one of the main advantages. Significant improvements in latency are obtained by using Xilinx tools and implementing this filter design in Verilog HDL. The Wallace tree multiplier is perfect for FIR filter construction in low-voltage and low-power VLSI applications since it has benefits like higher operating frequency and reduced power consumption. This development might improve the effectiveness and performance of digital filters, especially in settings with limited resources, opening the way for more robust VLSI systems

High Performance M-Term Karatsuba-Like Multiplier for Finite Field Arithmetic

Abstract: Finite field multiplication plays a crucial role in cryptographic circuits due to its widespread application. However, building circuits for these multiplications poses significant challenges due to their complexity. To mitigate this, the Karatsuba algorithm is employed, dividing each number into n/2 bits to reduce space complexity. While this approach reduces space complexity, it also increases time complexity. In our research, we introduce a hybrid approach, implementing a Karatsuba-like multiplier that combines elements of both Karatsuba and SBM (school book multiplication) techniques. Here in the proposed design, we replace the Array multiplier with a Wallace tree multiplier to further enhance design performance. This combination effectively reduces both time and space complexity. Our findings, based on reported device utilization and latency, demonstrate that the proposed multiplier outperforms the standard Karatsuba multiplier in terms of speed and efficiency, particularly in the area–delay product metric.

Design of efficient binary multiplier architecture using hybrid compressor with FPGA implementation

In signal processing applications, the multipliers are essential component of arithmetic functional units in many applications, like digital signal processors, image/video processing, Machine Learning, Cryptography and Arithmetic & Logical units (ALU). In recent years, Profuse multipliers are there. In that, Vedic multiplier is one of the high-performance multiplications and it is used to signal/image processing applications. In order to ameliorate the performance of this multiplier further, by proposed a novel multiplier using hybrid compressor. The proposed hybrid compressor-based multiplier is designed and implemented in Field programmable Gate Array (FPGA—spartan 6). The synthesis result shows that the speed of proposed hybrid compressor-based multiplier gets improved as compared to Array multiplier (35.83%), Wallace tree multiplier (34.58%), Vedic Multiplier based on Carry look ahead adder (CLA) (28.49%), Vedic Multiplier based on Ripple carry adder (RCA) (20.65%), Booth Multiplication (21.65%) and Vedic Multiplication based on Han-Carlson Adder (HCA) (20.10%) and Hybrid multiplier using Carry Select Adder (CSELA) (17.81%) and Hybrid Vedic Multiplier (7.15%).

FPGA-Based High-Speed Energy-Efficient 32-Bit Fixed-Point MAC Architecture for DSP Application in IoT Edge Computing

Designing high-speed and energy-efficient blocks for image and digital signal processing (DSP) architecture is an evolving research field. This work designs a high-speed and energy-efficient multiply-accumulate (MAC) unit to augment the performance of field-programmable gate array (FPGA)-based accelerators and softcore processors. In this work, three discrete 32-bit fixed-point signed MAC architectures were designed in Verilog and synthesized for the Zynq 7000 ZedBoard to obtain efficient MAC architecture. The ultimate goal of this work is to design a fast and energy-efficient MAC unit that can achieve speed up to the DSP48 block to reduce the latency of IoT edge computing. Energy efficiency was achieved in PPG and partial product addition (PPA) for the proposed Booth radix-4 Dadda (BR4D)-based MAC. At PPG, the width of the partial product (PP) terms was optimized with Bewick’s signed extension to reduce the power consumption. At PPA, the number of PP rows reduces the critical path delay (CPD) with Dadda-based PPA. The proposed BR4D MAC unit offers a reduction in dynamic power, CPD, power-delay product (PDP) and energy-delay product (EDP) by 22%, 9%, 29% and 36%, respectively, compared to standard Booth radix-4 Wallace tree (BR4WT) based MAC. Furthermore, hybrid MACs (BR4WT and BR4D) were compared with the current state-of-the-art (SoA) designs, and it was found that the proposed BR4D MAC is 47% faster compared to the same design in SoA. The proposed BR4D was tested for frequency scaling technique by reducing the frequency in steps of 10 MHz from a maximum usable frequency (MUF) of 64 MHz to 10 MHz to evaluate the performance for low-power applications. Reducing clock frequency by 84% will reduce the power consumption at the same proportion and speed by 38%. Additionally, the proposed design helps to improve the battery life of IoT end nodes with a reduction in energy consumption and EDP by 76% and 61%, respectively.

FPGA Implementation of Power-efficient Multipliers for Digital Signal Processing Applications

Background:: Higher power consumption raises chip temperature because it draws more current from the power source, which directly affects how long the batteries survive in portable devices. High temperature affects the dependability and functionality of a circuit, requiring more complex packaging and cooling strategies. One of the most significant challenges in VLSI design is power consumption. The power consumption of the circuit rises with both transistor density and chip complexity. In addition, one of the essential building blocks of hardware in the majority of VLSI applications and digital signal processing systems is the multiplier. Aims and objective:: This study aimed to design and compare array multiplier, Vedic multiplier, and Wallace tree multiplier using variable bit lengths. Methodology:: In this paper, authors designed array multiplier, Vedic multiplier, and Wallace tree multiplier using variable bit lengths. For comparison, the VIVADO tool was used to simulate and synthesize multiplier outputs. Results:: Wallace tree multipliers resulted in 31.153mW, 13.220mW, 4.099mW, and 0.988 mW of power dissipation for 16-bit, 8-bit, 4-bit, and 2-bit, respectively. The best multiplier was designed using different logic like AOI, OAI, NAND-NAND, and NOR-NOR and was compared based on power dissipation. It was observed that 2.256mW power dissipation was observed for NOR-NOR logic, which was minimal among other logics. Conclusion:: The 4-bit Wallace multiplier using NOR-NOR logic was used for FPGA implementation, which can be used in digital signal processing applications.

Enhancing multiplication efficiency: Harnessing Booth algorithm and Wallace tree synergy for 32-bit signed multipliers

This paper focuses on exploring performance optimization strategies for 32-bit signed multipliers in the realm of digital computation. The ingenious combination of the Booth algorithm and the Wallace tree takes center stage as the core of this research. Through a thorough analysis of this combined technique, the paper unveils its multifaceted advantages in multiplication operations. The unique contribution of the Booth algorithm is elaborately discussed, which involves streamlining the multiplication process by reducing the number of addition operations. Subsequently, the exceptional performance of the Wallace tree in accelerating the merging of partial products is highlighted. Through the synergistic interplay of these two techniques, the efficiency of multiplication operations is significantly enhanced, particularly suited for domains necessitating high-speed arithmetic computations, such as graphics processing and digital signal processing. The paper delves further into the significance of optimizing resource utilization, particularly in the field of integrated circuit design. By minimizing addition operations and optimizing parallel processing, the complexity of hardware implementation is reduced, leading to a notable decrease in resource requirements. This advantage proves invaluable in modern integrated circuit design, aiding designers in striking an optimal balance between spatial efficiency and power consumption.

Enhancing ASIC chip performance through integrated algorithm optimization

As a crucial arithmetic logic unit, the multiplier plays a significant role in digital signal processing. However, multiplication operations often require a large number of calculations and logic gates, leading to increased circuit complexity and power consumption. To enhance the performance and efficiency of multipliers, this paper presents an optimization analysis based on the Wallace Tree and Booth algorithms. The Wallace Tree algorithm decomposes multiplication operations into multiple stages and employs both separate operations and bit-level parallelism to accelerate multiplication, achieving efficient parallel multiplication computations and reducing both latency and area complexity of multiplication. On the other hand, the Booth algorithm is an optimization method for signed binary multiplication. By introducing the concept of Booth encoding, it transforms signed multiplication into unsigned multiplication, thereby reducing the number of multiplication operations. This paper analyses the application and research progress of the Wallace Tree and Booth algorithms in the field of multiplier optimization to improve computational speed and reduce power consumption of multipliers.

16-Bit multiplier optimization based on Wallace tree and Booth algorithm

With the expanding computer application scenarios and increasing computational demands, optimizing 16-bit multiplication is an important and meaningful research topic. In this paper, we take advantage of the parallel computing property of Wallace tree and the advantage of bit-level operation of Booth algorithm to perform certain optimization on 16-bit multiplier. In this paper, a series of basic modules are firstly constructed as the basic framework of the multiplier, and then the optimization module is designed by using Booth algorithm and Wallace tree, and they are combined to obtain a multiplier with improved computational accuracy, reduced computational complexity, reduced delay, and improved computational efficiency compared with the traditional multiplier. The significance of the optimized multiplier implementation is to increase the computational speed, improve the chip resource utilization, reduce the power consumption and energy consumption, and meet the demand of complex applications, which is of great significance to improve the performance and efficiency of computer systems.

A design of multiplier based on Radix_4 Booth algorithm and 4-2 Wallace compression tree

In a multitude of computational and signal processing scenarios, the multiplier functions as a fundamental arithmetic component. Given the complex hardware arrangement of multipliers and their usual positioning within the crucial pathway of digital systems, their significance is substantial. Therefore, approximations of multipliers can greatly optimize system performance. This essay examines the fundamental ideas behind the Wallace tree, the Carry ahead adder, and the Radix-4 Booth algorithm. Additionally, instead of the more common 3-2 compressors, a Wallace tree structure with 4-2 compressors is used to compact these products for the manufacture of partial products. This reduction in compression stages to three significantly curtails delays along critical paths, thereby substantially improving overall performance. The compressed outcomes from the Wallace tree undergo processing via a 64 bit carry ahead adder, effectively addressing delays stemming from mutual carry propagation among sequentially connected regular full adders. Leveraging these principles and processes, a 32-bit signed multiplier is designed. Building upon this foundation, an approximate Booth multiplier is developed, enhancing both computational speed and reducing critical path delays. The functionality of the multiplier was validated using Vivado simulation, demonstrating its correctness. Additionally, the RTL-level circuitry of different segments of the multiplier was showcased.

Optimizing multiplier design for enhanced processor performance

In processor design, the multiplier serves as a critical component whose operational speed and efficiency directly impact the performance of the processor. To meet the demands of rapidly advancing technology, enhancing processor performance is of paramount importance. The crux of multiplier design lies in reducing the count of partial products and compressing them. This paper presents the design of a multiplier that utilizes the Booth algorithm and the Wallace tree structure for optimization, along with the incorporation of registers for secondary pipeline processing to further elevate efficiency. The Booth algorithm selects the base-4 Booth algorithm, effectively reducing the count of partial products and mitigating the optimization efficiency reduction caused by circuit complexity. The Wallace tree structure employs a combination of 3-2 and 4-2 compressors, resulting in decreased resource consumption and reduced critical path delays. This paper outlines a step-by-step introduction to these three optimization methods and conducts simulations and tests on the current multiplier after each optimization step. Through simulation analysis, this paper confirms the success of the design and provides insights and outcomes to the current field of multiplier optimization, aiming to ultimately drive advancements in processor performance.

Enhancement Of A 32-By-32-Bit Signed Digital Multiplier: A Multi-Dimensional Optimization Approach

In the pursuit of enhanced performance in a 32-by-32-bit signed digital multiplier, optimizations were enacted on three critical fronts. Initial efforts focused on the integration of an advanced Booth encoding technique for the generation of three-bit control signals, meticulously crafted in the Verilog programming language. This approach, characterized by its restricted symbol expansion methodology, strategically curtails hardware resource expenditures, and diminishes power utilization during computational tasks. Subsequently, a sophisticated hybrid Wallace tree architecture was employed, offering a notable decrement in the delay of two XOR gates in contrast to the exclusive application of 3-2 and 4-2 compressors. This refinement not only augments the aggregation efficacy of partial products but also substantially accelerates operational velocity. Furthermore, the incorporation of a 64-bit carry-lookahead adder was instrumental in mitigating the latency induced by lower-order carry anticipation. To ascertain the multiplier's computational precision, a Verilog-constructed testbench file facilitated the assembly of 100,000 test vectors, with simulations executed in ModelSim yielding a verifiable accuracy rate of 100%.

Area and delay efficient RNS-based FIR filter design using fast multipliers

In today's digital age, speed, and area are the primary design concerns. Increasing the rate at which multiplication and addition are performed has always been a need for developing cutting-edge technologies. Wallace multipliers, and Dadda multipliers, are one of the fastest multipliers used in many processors to accomplish fast arithmetic operations. A novel approach to design a LookUp Table (LUT) multiplier was proposed and implemented in Finite Impulse Response (FIR) filter. To improve the Residue Number System (RNS) based FIR filter's performance, several adders like Carry Look ahead (CLA) adder, Kogge Stone adder (KSA) and proposed adder architectures have been implemented. When compared with the 16 tap with 32 bit proposed adder with LUT multiplier, the hardware resource utilization (Logic Elements) is decreased by 5.97 % and in 32 tap with 16 bit combination, it decreases by 7.60 %.When compared with 32 tap with 4 bit word length, the proposed adder with LUT multiplier in the highlighted combinations, the Fmax is increased by 19.28 % and in 32 tap with 16 bit, it increases by 29.74 %. The Low-pass RNS FIR filter is designed for a cut-off frequency of 50 Hz and generated filter coefficients in MATLAB and implemented to denoising the ECG signal.

ASIC implementation of ECG denoising FIR filter by using hybrid Vedic–Wallace tree multiplier

AbstractThe design of hand‐held portable devices for cardiovascular health monitoring based on the analysis of electrocardiogram (ECG) is a hot topic of research nowadays. Digital filters, possibly designed using digital multipliers, are a critical module in the design of such analysis systems. This paper presents the ASIC design of a 64th‐order digital low‐pass FIR filter to be used in ECG denoising applications. The FIR filter is optimized for usage in battery‐operated portable systems, wherein power consumption and on‐chip area are crucial parameters of concern. These challenges are met by employing a novel multiplier architecture, which we design by hybridizing the two popular digital multiplication algorithms, namely, the Vedic multiplication algorithm and the Wallace tree multiplication algorithm. The proposed multiplier consumes lower area and power consumption than either of the aforementioned conventional multiplication algorithms. This is established through FPGA‐based implementations on Artix‐7 FPGA, for the various wordlengths. The area and power optimizations are further exercised by two proposed techniques, namely, elimination of redundant multipliers, and power gating using the proposed zero‐detector circuit. RTL‐to‐GDSII flow has been completed using Cadence digital design and sign‐off tools for SCL 180 nm technology. The results indicate that the proposed filter architecture occupies 16.38% lower area and 79.58% lower power consumption than the contemporary designs described in the literature.

FPGA design of FFT based intelligent accelerator with optimized Wallace tree multiplier for image super resolution and quality enhancement

The super-resolution (SR) method has been widely used to improve the resolution and quality of natural images, and it is currently being employed in medical imaging. Recently, many techniques have been introduced by researchers to improve the resolution and quality of the image. However, these approaches generate blurring and jagged edges in images. Hence, this article introduces novel deep learning (DL) with a fast Fourier transform (FFT) based intelligent approach (IA) to improve the quality and resolution of the image. A convolutional neural network (CNN) is emphasized for quality enhancement and resolution to recover lost information during image acquisition. This work undergoes three significant stages: de-noising, segmentation, and resolution improvement of the noisy input image. The double density discrete wavelet transform (DDDWT) technique is introduced to remove the noise and improve the visual image’s quality. Finally, the image resolution and quality enhancement are done using CNN with overlap and add (OA)-FFT based Wallace tree multiplier-red deer optimization (WT-RDO) technique. In the experimental scenario, the quality enhancement and image resolution outcome achieved accuracy of 97 % and 98 %, precision of 97 % and 97 %, sensitivity of 96 % and 98 %, specificity of 96 % and 98 %, PSNR of 30 dB and 26 dB, structural similarity index (SSIM) of 0.86 and 0.85, mean square error (MSE) of 0.01, mean absolute error (MAE) of 0.8, the time complexity of 61, power of 0.08 W, delay of 0.6 ns and throughput of 3.2 MB/s.

Efficient Design of Modified Wallace Tree Approximate Multipliers Based on Imprecise Compressors for Error-Tolerance Applications

Efficient Design of Modified Wallace Tree Approximate Multipliers Based on Imprecise Compressors for Error-Tolerance Applications

Low Power Wallace Multiplier Using Gate Diffusion Input Based Full Adders

Now a days, in CMOS circuits leakage power is becoming more and more remarkable in power dissipation. Digital signal processing performs many functions including multiplication which is the prominent one. In the design of energy efficient processor multipliers play a key role in which it determines the DSP processor efficiency. A 4*4Wallace tree multiplier employs gate diffusion input technique to minimize leakage power. It is designed by adopting one bit full adder. In the proposed method, full addersare replaced by4*4 Wallace tree multiplier. Power dissipation majorly occurs in full adders. Hence, minimizing power dissipation in full adders will shrink dissipation of power in multipliers. Here, the proposed work diminishes the leakage power in comparison with the existing method.