Wafer Warpage Research Articles

Low Stress and High Ductility Copper Electroplating Additive Development

Due to cost concerns, significant changes have been made in the silicon manufacturing process leading to thinner Si wafers. This change brings many challenges for copper metallization. One of the biggest challenges is to maintain low internal stress of the copper deposit. This is key to avoid solar wafer warpage and maintain good adhesion. Copper deposits with high ductility are also desired to prevent or reduce the potential for the copper deposit to crack under stress over time. Ideal copper deposits exhibit low internal stress and high ductility. However, development of this plating chemistry is a challenge, as improvement in one attribute typically comes at the expense of another. In this paper, the performance of new acid copper electroplating bath capable of achieving both low internal stress and good ductility will be highlighted. Additive impact on copper deposit material properties and correlation between these properties and performance will be discussed.

Low Stress and High Ductility Copper Electroplating Additive Development

Copper electroplating is one of the most important metallization technologies to produce metal contacts in the fabrication of crystalline silicon solar cells. It has been adopted in three areas, including: Interdigited Back Contact cell (IBC); Heterojunction with Intrinsic Thin layer (HIT); and Fully Plated Front Contact solar cells. Due to cost concerns, significant changes have been made in the silicon manufacturing process leading to thinner Si wafers. This change brings many challenges for copper metallization. One of the biggest challenges is to maintain a low internal stress of the copper deposit. This is key to avoid solar wafer warpage and maintain good adhesion. Copper deposits with high ductility are also desired to prevent or reduce the potential for the copper deposit to crack under stress over time. Ideal copper deposits exhibit low internal stress and high ductility. However, development of this plating chemistry is a challenge for the material supplier, as improvement in one attribute typically comes at the expense of another. Accordingly, there is need to develop organic additives for copper electroplating baths that alleviate internal stress in copper deposits as well as providing good ductility. In this paper, the performance of new acid copper electroplating bath capable of achieving both low internal stress and good ductility will be highlighted. Additive impact on copper deposit material properties and correlation between these properties and performance will be discussed

Porous Silicon in Microelectronics: From Academic Studies to Industry

Historically, electronics was the first discipline that sought to exploit the properties of porous silicon (PSi) in the 70’s [1]. Thereafter, the capability of PSi to be used, after full oxidation, to isolate bipolar devices was pointed out. Two decades later, radio-frequency (RF) devices also took advantages of the isolating properties of PSi [2]. Indeed, highly resistive substrates are generally required to reduce eddy currents and capacitive couplings and then, to get high performance passive devices. The insulating properties of PSi, combined with the ability to locate these areas in different resistivity wafers, make this material promising in terms of development of monolithic insulator/semiconductor substrates. Recently, at GREMAN, we demonstrated the improvement of RF functions using large area hybrid substrates on which filters and protection diodes were integrated [3]. Nowadays, efforts are also made in order to stabilize the structure using appropriate post-anodization treatments. PSi magnetic functionalization studies are also in progress in order to improve integrated planar inductor performances. Through collaboration between GREMAN and STMicrolectronics, the way PSi could be used as insulated material in power AC Switch is also investigated. Many architectures involving PSi peripheries can lead to subsequent performance and reliability improvements [4,5,6]. At present, there is no doubt about benefits PSi can bring to microelectronic devices. Many other applications such as integrated sensors [7], solar cells [8], conductive vias [9] or energy microsources [10,11] can also be of a great interest for the microelectronics industry. Nevertheless, until now, PSi is not yet introduced in the field of electronic component manufacturing. Chips manufacturers are still reluctant to invest in this technology. Indeed, acceptance of a new technology associated to new equipment takes time. For example the deep reactive-ion etching took 20 years to reach an installed base of 1000 chambers worldwide. Robert Bosch GmbH is the only currently known big player company using PSi on an industrial scale for the production of pressure sensors [12]. For the sake of the PSi introduction in this field, it is necessary to develop and validate reliable equipments and processes in terms of throughput but also in terms of homogeneous PSi characteristics at wafer level (up to 6 and 8 inches wafer levels). In this paper, we show also recent advances in the field of PSi etching and integration at an industrial level. In particular, we put an emphasis on reproducibility and homogeneity issues, on the wafer warp management using different annealing procedures and the optimization of the electrolyte composition and its ageing.

New Stacked Die Interconnect Technology for High-Performance and Low-Cost FPGA

This article introduces the first comprehensive demonstration of new innovative technology comprising multiple key technologies for highly cost-effective and high-performance Xilinx field programmable gate array (FPGA), which is so-called stack silicon-less interconnect technology (SLIT) that provides the equivalent high-bandwidth connectivity and routing design-rule as stack silicon interconnect (SSI) technology at a cost-effective manner. We have successfully demonstrated the overall process integration and functions of our new SLIT-employed package using Virtex®-7 2000T FPGA product with chip-to-wafer stacking, wafer-level flux cleaning, microbump underfilling, mold encapsulation, and backside silicon removal. Of all technology elements, both full silicon removal process with faster etching and no dielectric layer damage and wafer warpage management after full silicon etching are most crucial elements to realize the SLIT technology. To manage the wafer warpage after full Si removal, a couple of knobs are identified and used such as top reinforcement layer, microbump underfill properties tuning, die thickness, die-to-die space, and total thickness adjustments. It is also discussed in the article how the wafer warpage behaves and how the wafer warpage is managed. New SLIT module shows excellent warpage characteristics of only −30 μm ∼ −40 μm at room temperature (25°C) for 25 mm × 31 mm in size and +20 μm ∼ +25 μm at reflow temperature (250°C). Thermal simulation results shows that thermal resistance of new SLIT package is almost comparable to that of standard 2000T flip-chip ball grid array (FC-BGA) package using through silicon via interposer with standard heat sink configuration and air wind condition. The reliability assessment is now under the study.

Elimination of stress induced dislocation in deep Poly Sinker LDMOS technology

This work investigates the leakage current of power LDMOS (laterally diffused metal–oxide–semiconductor) transistors with deep poly sinker, and the leakage shows a certain wafer map distribution with most of the failed dies located at the center area. It is found that the leakage current is mainly caused by the stress-induced dislocations close to the deep poly sinker. The relationship between the stress-induced dislocation (SID) and the wafer warpage is studied. Experimental results show the dislocation and the resulting leakage current can be effectively eliminated, by either modifying the device layout or optimizing the fabrication process of the poly sinker.

MOCVD of GaN-based HEMT structures on 8 inch silicon substrates

ABSTRACTMetal organic chemical vapor deposition, as well as material and basic device properties of nitride-based high electron mobility transistor structures on (111) silicon substrates varying in diameter from 4 to 8 inch were studied using in-situ and ex-situ characterization techniques. All substrates used for the growth of the nitride structures in this study were of SEMI standard thicknesses. The total thickness of the nitride structures was in the range of 1.5 – 5 µm. It is reported that nitride structures can be grown on 4, 6 and 8 inch diameter substrates with very similar post-growth wafer shape, material and device characteristics. It is also shown that their crystal quality, 2DEG transport properties and isolation blocking voltages can be improved by increasing nitride structure thickness while maintaining post-growth wafer bow and warp less than 50 µm. The maximum thickness of nitride structures that can be successfully grown on 8 inch diameter SEMI standard substrates seems to be limited to about 4.5 µm due to plastic deformation of Si. Blocking voltages of more than 700 V were achieved using 4.5 µm thick nitride-based high electron mobility transistor structures grown on 8 inch Si substrate.

실리콘 웨이퍼 휨형상 측정 정밀도 향상을 위한 시스템변수 보정법

ABSTRACT As a result of a mismatch of the residual stress between both sides of the silicon wafer, which warps and distorts during the patterning process. The accuracy of the warpage measurement is related to the calibration. A CCD camera was used for the calibration. Performing optimization of the error function constructed with phase values measured at each pixel on the CCD camera, the coordinates of each light source can be precisely determined. Measurement results after calibration was performed to determine the warpage of the silicon wafer demonstrate that the maximum discrepancy is 5.6 with a standard deviation of 1.5 in comparison with the test results obtained by using a Form TalySurf instrument. Key Words : silicon wafer(실리콘웨이퍼), warpage measurement(휨형상 측정), CCD camera(카메라), Fringe pattern(간섭무늬 패턴), calibration(보정), system parameter(시스템변수) *School of Mechanical Engineering, KYUNGNAM UNIV.# Corresponding Author : School of Mechanical Engineering, KYUNGNAM UNIV. E-mail : bckim@uok.ac.kr

Wafer level Cu–Cu direct bonding for 3D integration

Wafer level bonding and stacking process for 3D stacked IC was proposed and technical issues were discussed. Cu bumps surrounded by recessed SiO2 were thermo-compression bonded and electrically evaluated using Kelvin structures. Defects at the bonding interface such as voids were responsible for electrical resistance distribution. Wafer alignment during stacking process was found to be affected by several factors like non-uniform bump height, the spacers in a bonding fixture and wafer warpage. Step by step warpage measurement revealed that the wafer warpage was dependent on process steps and worsened at bonding step.

A novel mechanical diced trench structure for warpage reduction in wafer level packaging process

The wafer warpage problem, mainly originated from coefficient of thermal expansion mismatch between the materials, becomes serious in wafer level packaging as large diameter wafer is adopted currently. The warpage poses threats to wafer handling, process qualities, and can also lead to serious reliability problems. In this paper, a novel mechanical diced trench structure was proposed to reduce the final wafer warpage. Deep patterned trenches with a depth about 100μm were fabricated in the Si substrate by mechanical dicing method. Both experiment and simulation approaches were used to investigate the effect of the trenches on the wafer warpage and the influence of the geometry of the trenches was also studied. The results indicate that, by forming deep trenches, the stress on the individual die is decoupled and the total wafer warpage could be reduced. The final wafer warpage is closely related to the trench depth and die width. Trenched sample with a depth of 100μm can decrease the wafer warpage by 51.4%.

종자결정을 활용한 다결정 규소 잉곳 내의 구조적 결함 규명

Because of the temperature gradient occurring during the growth of the ingot with directional solidification method, defects are generated and the residual stress is produced in the ingot. Changing the growth and cooling rate during the crystal growth process will be helpful for us to understand the defects and residual stress generation. The defects and residual stress can affect the properties of wafer. Generally, it was found that the size of grains and twin boundaries are smaller at the top area than at the bottom of the ingot regardless of growth and cooling condition. In addition to that, in the top area of silicon ingot, higher density of dislocation is observed to be present than in the bottom area of the silicon ingot. This observation implies that higher stress is imposed to the top area due to the faster cooling of silicon ingot after solidification process. In the ingot with slower growth rate, dislocation density was reduced and the TTV (Total Thickness Variation), saw mark, warp, and bow of wafer became lower. Therefore, optimum growth condition will help us to obtain high quality silicon ingot with low defect density and low residual stress.

Warping of silicon wafers subjected to back-grinding process

This study investigates warping of silicon wafers in ultra-precision grinding-based back-thinning process. By analyzing the interactions between the wafer and the vacuum chuck, together with the machining stress distributions in damage layer of ground wafer, the study establishes a mathematical model to describe wafer warping during the thinning process using the elasticity theory. The model correlates wafer warping with machining stresses, wafer final thickness, damage layer thickness, and the mechanical properties of the monocrystalline silicon. The maximum warp and the warp profile are measured on the wafers thinned to various thicknesses under different grinding conditions, and are used to verify the modeling results.

Cost Effective and High Performance 28nm FPGA with New Disruptive Silicon-Less Interconnect Technology (SLIT)

This paper introduces the first comprehensive demonstration of new disruptive innovation technology comprising multiple Xilinx patent-pending innovations for highly cost effective and high performance Xilinx FPGA, which is so called stack silicon-less interconnect technology (SLIT) that provides the equivalent high-bandwidth connectivity and routing design-rule as stack silicon interconnect (SSI) technology at a cost-effective manner. We have successfully demonstrated the overall process integration and functions of our new SLIT-employed package using Virtex® -7 2000T FPGA product. Chip-to-Wafer stacking, wafer level flux cleaning, micro-bump underfilling, mold encapsulation are newly developed. Of all technology elements, both full silicon etching with high etch selectivity to dielectric/fast etch rate and wafer warpage management after full silicon etching are most crucial elements to realize the SLIT technology. In order to manage the wafer warpage after full Si removal, a couple of knobs are identified and employed such as top reinforcement layer, micro-bump underfill properties tuning, die thickness/die-to-die space/total thickness adjustments. It's also discussed in the paper how the wafer warpage behaves and how the wafer warpge is managed. New SLIT module shows excellent warpage characteristics of only −30 μm ~ −40 μm at room temperature for 25 mm × 31 mm in size and +20 μm ~ +25 μm at reflow temperature. Thermal simulation results shows that thermal resistance of new SLIT package is almost comparable to that of standard 2000T FCBGA package using TSV interposer with standard heat sink configuration and air wind condition. The reliability assessment is now under the study.

A Novel Thin Wafer Handling Technology to Enable Cost-Effective Fabrication of Through-Glass Via Interposers

Thin wafer handling technologies to fabricate silicon interposers have been widely discussed at conferences. Despite tremendous efforts to overcome several technical hurdles such as wafer chipping, cracking, and warpage, high manufacturing costs resulting from the complexity of the processes used to make silicon interposers remains a major concern. Fabricating a through-glass via (TGV) interposer using novel thin wafer handling (TWH) technology will be presented here as an example of a simple and cost-effective solution for realizing 2.5-D IC integration. Utilizing a simplified TWH technology, a TGV interposer with 30-μm-diameter vias to eliminate the isolation layer is combined with polymer-based polybenzoxazole (PBO) as passivation to build one to two redistribution layers (RDLs) with 20-μm line width on both sides after thinning to 100 μm. The simplified TWH requires only a release layer on the glass carrier and another layer of bonding material on the TGV wafer to enable fabrication of a TGV interposer. A process flow for fabricating a TGV interposer utilizing a simplified TWH technology will be presented in detail, including carrier treatment, bonding material, bonding, titanium/copper seed layer deposition, copper plating, RDL deposition, under-bump material (UBM) formation, debonding, and silicon chip stacking on a TGV interposer. The combination of TGV interposer and novel TWH technology will pave the way for cost-effective fabrication in 2.5-D IC.

Influence of the Viscoelastic Properties of the Polyimide Dielectric Coating on the Wafer Warpage

Polyimide is widely used as the dielectric material in wafer level packaging. One potential problem with its application is the warpage and stress generated in the curing process. This paper investigated the material properties of polyimide and its influence on the wafer warpage. The viscoelastic properties of polyimide film were measured and a mathematical model of the properties was developed. Finite element analysis of the wafer warpage was performed and this indicates that the viscoelastic material model gave the best prediction. To better understand the causation of the warpage, curvature evolution of the polyimide-coated silicon wafer during its curing process was measured by a multi-beam optical sensor system. It was found that the warpage was mainly induced by the coefficient of thermal expansion mismatch and that the cure shrinkage of polyimide had little effect. Additionally, the effect of the cooling rate on the wafer warpage was also studied. Both simulation and experiment results showed that a slower cooling rate in the temperature range around the glass transition temperature (T g) of polyimide will help to reduce the final wafer warpage.

Finite-Element Simulation of Different Kinds of Wafer Warpages: Spherical, Cylindrical, and Saddle

During the wafer fabrication process, wafers warp into different kinds of shapes, such as spherical, cylindrical, or saddles. These wafers may exhibit a bistable state, that is, if we apply a certain amount of pressure, they snap into another state. Though these shapes are commonly observed in the real world, we have found that it is extremely difficult to obtain these shapes in finite-element tools, such as ANSYS, because some of these states are not numerically preferred solutions. In this paper, we discuss various methodologies we have used to obtain these shapes in ANSYS. The experiments have been carried out in our fabrication lab to measure the wafer warpage at various stages of wafer fabrication. We have found that when the simulated shape matches the experiment, the warpage or maximum out of plane displacement of the wafer obtained from our simulation matches with 1% with the experimental results as well. Furthermore, ANSYS simulations show that backgrinding increases the warpage by the same amount as observed in the experiments. This paper also discusses the limitations of Stoney's formula. The final goal of this paper is to predict how warpage is going to affect the stresses in the silicon (Si) trenches in a device and if any particular trench design is going to lower the amount of wafer warpage, hence the stresses in Si trenches. Section IV shows the simulation results of stresses in the Si trenches. Since it would be computationally infeasible to model a full wafer having all the details of the trench structures, a submodeling technique has been adopted to calculate the stresses in the Si trench wall of a warped wafer. These simulation results are compared with micro-Raman spectroscopy measurements of a warped wafer.

Analysis of Asymmetric Warpage of Thin Wafers on Flat Plate Considering Bifurcation and Gravitational Force

Large deformation of thin silicon wafer on flat plate induced by film stress was analyzed by analytic method and finite element analysis (FEA) method considering bifurcation and gravitation. Bifurcation criterion was obtained by energy method, and resulting warpage was calculated from obtained curvature. Anisotropy of substrate and film material was considered. For simple cases where mismatch strain was isotropic but the silicon substrate was anisotropic, explicit expression of the bifurcation criterion was obtained. Material anisotropy made great effect on the criterion for (100) wafer. It was almost always in the bifurcation state when the wafer was thinned for packaging process. FEA models to analyze bifurcation were investigated. Gravitational force accompanying with the contact between the flat plate and the silicon wafer were applied. A carefully chosen quarter-model rotated by 45 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> was sufficient to analyze the warpage behavior. Bending down by gravitational force and nonuniform curvature over the wafer were observed. Two FEA schemes were proposed. One was combination of buckling and postbuckling analysis. The other was the force or moment perturbation method. Both methods well described the warpage considering bifurcation and gravitation, and reached the same result.

Experimental Study on Temperature during Wire Saw Slicing

Heat generated during wire saw slicing can cause silicon temperature raise and make silicon wafer warpage, especially for larger silicon wafers. In order to study the wire saw effect on silicon temperature during slicing process, three kinds of wire saw, mainly semi-fixed abrasive wire saw and traditional wire saw, are applied for slicing silicon ingot. In this paper, the thermocouple is used to measure the temperature of the silicon during wire saw slicing. The experiment results show that the temperature of the silicon increases along with the wire saw working direction and reaches maximum value near the outlet position of silicon. The temperature of the silicon sliced by semi-fixed abrasive wire saw is lower than that sliced by traditional wire saw.

웨이퍼 레벨 적층 공정에서 웨이퍼 휘어짐이 정렬 오차에 미치는 영향

본 연구에서는 웨이퍼 레벨 적층 과정에서 발생하는 웨이퍼 오정렬(misalignment) 현상과 웨이퍼 휘어짐(warpage)과의 관계에 대해서 조사하였다. <TEX>$0.5{\mu}m$</TEX> 두께의 구리 박막 증착을 통해 최대 <TEX>$45{\mu}m$</TEX>의 휨 크기(bow height)를 갖는 웨이퍼를 제작하였으며, 이 휘어진 웨이퍼와 일반 웨이퍼를 본딩하였을 때 <TEX>$6{\sim}15{\mu}m$</TEX> 정도의 정렬 오차가 발생하였다. 이는 약 <TEX>$5{\mu}m$</TEX>의 웨이퍼 확장(expansion)과 약 <TEX>$10{\mu}m$</TEX>의 미끄러짐(slip)의 복합 거동으로 설명할 수 있으며, 웨이퍼 휘어짐의 경우 확장 오정렬보다 본딩 과정에서의 미끄러짐 오정렬에 주로 기여하는 것으로 보인다. In this study, the effects of wafer warpage on the misalignment during wafer stacking process were investigated. The wafer with <TEX>$45{\mu}m$</TEX> bow height warpage was purposely fabricated by depositing Cu thin film on a silicon wafer and the bonding misalignment after bonding was observed to range from <TEX>$6{\mu}m$</TEX> to <TEX>$15{\mu}m$</TEX>. This misalignment could be explained by a combination of <TEX>$5{\mu}m$</TEX> radial expansion and <TEX>$10{\mu}m$</TEX> linear slip. The wafer warpage seemed to be responsible for the slip-induced misalignment instead of radial expansion misalignment.

Development of a Measuring Equipment for Silicon Wafer Warp

Larger diameter wafers are used to decrease the cost of IC manufacturing and the wafer thickness is decreasing for form factor and thermal power dissipation considerations. The larger wafer requires a large scanning area to inspect the warp, and warp measurement of large and thin silicon wafers is greatly affected by the gravity-induced deflection. In this paper the gravity-induced deflection was calculated using finite element method by supporting the wafer horizontally with three steel balls. A laser displacement sensor based on triangulation principle was used to measure the warp and an air bearing stage was developed to achieve high straightness. The shape of the wafer was obtained using the silicon wafer warp measuring equipment.

Warpage Simulation by the CTE mismatch in Blanket Structured Wafer Level 3D packaging

In 3D wafer-stacking technology, one of the major issues is wafer warpage. Especially, The important reason of warpage has been known due to CTE(Coefficient of Thermal Expansion) mismatch between materials. It was too hard to choose how to make the FE model for blanket structured wafer level 3D packaging, because the thickness of each layer in wafer level 3D packaging was too small (micro meter or nano meter scale) comparing with diameter of wafer (6 or 8 inches). In this study, the FE model using the shell element was selected and simulated by the ANSYS WorkBench to investigate effects of the CTE on the warpage. To verify the FE model, it was compared by experimental results.