Wafer level Cu–Cu direct bonding for 3D integration

Abstract

Wafer level bonding and stacking process for 3D stacked IC was proposed and technical issues were discussed. Cu bumps surrounded by recessed SiO2 were thermo-compression bonded and electrically evaluated using Kelvin structures. Defects at the bonding interface such as voids were responsible for electrical resistance distribution. Wafer alignment during stacking process was found to be affected by several factors like non-uniform bump height, the spacers in a bonding fixture and wafer warpage. Step by step warpage measurement revealed that the wafer warpage was dependent on process steps and worsened at bonding step.