New Stacked Die Interconnect Technology for High-Performance and Low-Cost FPGA

Abstract

This article introduces the first comprehensive demonstration of new innovative technology comprising multiple key technologies for highly cost-effective and high-performance Xilinx field programmable gate array (FPGA), which is so-called stack silicon-less interconnect technology (SLIT) that provides the equivalent high-bandwidth connectivity and routing design-rule as stack silicon interconnect (SSI) technology at a cost-effective manner. We have successfully demonstrated the overall process integration and functions of our new SLIT-employed package using Virtex®-7 2000T FPGA product with chip-to-wafer stacking, wafer-level flux cleaning, microbump underfilling, mold encapsulation, and backside silicon removal. Of all technology elements, both full silicon removal process with faster etching and no dielectric layer damage and wafer warpage management after full silicon etching are most crucial elements to realize the SLIT technology. To manage the wafer warpage after full Si removal, a couple of knobs are identified and used such as top reinforcement layer, microbump underfill properties tuning, die thickness, die-to-die space, and total thickness adjustments. It is also discussed in the article how the wafer warpage behaves and how the wafer warpage is managed. New SLIT module shows excellent warpage characteristics of only −30 μm ∼ −40 μm at room temperature (25°C) for 25 mm × 31 mm in size and +20 μm ∼ +25 μm at reflow temperature (250°C). Thermal simulation results shows that thermal resistance of new SLIT package is almost comparable to that of standard 2000T flip-chip ball grid array (FC-BGA) package using through silicon via interposer with standard heat sink configuration and air wind condition. The reliability assessment is now under the study.