Surface Roughness Of Wafer Research Articles

Experiment study on electroplated diamond wire saw slicing single-crystal silicon

This paper conducted the slicing experiments of single-crystal silicon using a reciprocating electroplated diamond wire saw. The machined wafer topography and wire wear were observed by using scanning electron microscope (SEM). The influences of process parameters and cutting fluids on single-crystal silicon wafer surface roughness (SR), subsurface micro-crack damage (SSD) depth, total thickness variation (TTV) and warp were investigated. The bonded interface sectioning technique was used to examine the cut wafers SSD depth. Study results show that a higher wire speed and lower ingot feed speed can produce lower wafer SR and SSD; the lower warp of wafer needs lower wire speed and ingot feed speed; and low wafer TTV can be obtained by an appropriate matching relationship between wire speed and ingot feed speed. The synthetic cutting fluid has a better total effect to improve the wafer quality. The pulled-out of diamond abrasives is the main wear form of wire, which indicates that more research on improving the abrasives retaining strength on wire surface should be investigated in fixed-abrasive wire manufacturing process, in order to improve the wire life and wire saw machining process.

Effect of wear of diamond wire on surface morphology, roughness and subsurface damage of silicon wafers

Wear of fixed abrasive diamond wire affects the quality of sliced silicon wafers, necessitating replacement of the costly wire. This paper analyzes the effect of wire wear on the surface morphology, roughness, and subsurface damage of as-cut single crystal silicon wafers. Scanning electron microscopy, Raman spectroscopy, confocal microscopy, focused ion beam machining (FIB), and biaxial flexure are used to evaluate the surface morphology, areal surface roughness, and subsurface damage (cracks). Results show that, with increased wire wear, the wafers exhibit greater evidence of ductile removal, lower surface roughness, fewer but slightly deeper subsurface cracks, and lower average fracture strength.

A high efficiency industrial polysilicon solar cell with a honeycomb-like surface fabricated by wet etching using a photoresist mask

In this paper, an effective and low cost method of texturization was introduced into the fabrication process for industrial multicrystalline silicon solar cell production. The purpose of the method was to reduce reflectance by creating a honeycomb-like textured surface using a masked wet etching process. A negative photoresist film was selected as an etching mask. Although large surface roughness of wafer was considered to affect the adhesion and acid resistance of etching mask, a honeycomb-like textured surface with a pitch of 18μm was fabricated successfully. The etched pits had a nearly smooth spherical segment surface, an average aperture of 15.1μm, and a depth of 6.5μm. This regular textured surface had a low light reflectivity of approximately 20.5% and greatly increased the carrier lifetime. Compared with multicrystalline silicon solar cells textured by conventional acid etching, the average short circuit current increased by 2.2% and the average efficiency increased from 17.41% to 17.75%, a net gain of 0.34%. And a high throughput above 2400 pieces per hour was obtained. This texturing technique is expected to promote the application of diamond-wire cut multicrystalline silicon wafers with the low saw-damage in the future.

Ultra-Fast SiC Wafer Surface Roughness Mapping

SiC wafer surface roughness is known to affect the electrical properties of certain power devices. As a result, inspection of the surface roughness can be a very important step for SiC device manufacturing processes. In this paper, we propose a newly fast surface roughness measurement method using Differential Interference Contrast (DIC) microscopy image. Results from this method were compared against white-light interference measurement system and a good correlation was confirmed. The comparison result confirmed that this method was a valid method to measure the surface roughness. This method enables users to inspect the surface roughness in 5 minutes (100mm wafer) and 10 minutes (150mm wafers), respectively.

Influence of fixed abrasive configuration on the polishing process of silicon wafers

Lapping and polishing with fixed abrasives is an efficient method to flatten wafers and obtain mirror surface finish. One of the most concerned things is abrasive configuration for polishing pads in research. Researching on pad’s abrasive configuration will help get better wafer surface quality. For abrasive trajectories can heavily affect wafer surface flatness and roughness during lapping and polishing process, the present work was conducted to study the relationship among abrasive configuration, trajectory distribution, material removal, and its influence on wafer surface quality. For this purpose, an abrasive configuration method was applied by adopting a written Matlab program to give set values of the radial distance and the initial angle of abrasives fixed on the pad surface. Based on the method, polishing pads with the regular and radial configurations were designed and used to study trajectory distributions under different polishing parameters. The polishing experiments were carried out on silicon wafers with the regular and the radial diamond polishing pads made by the sol-gel method. The wafer surface morphology, thickness, and roughness were detected in polishing. The results show that better flatness and roughness distributions can be obtained through using the radial pad than that of the regular pad, which is due to the smaller value of variation coefficient of the standard deviation for trajectory density and better global profile of trajectory density. The method of pad design and trajectory analysis can be an effective way to design pads with proper abrasive configurations for different applications in lapping and polishing process.

Study on Sapphire Wafer Grinding by Chromium Oxide (Cr<sub>2</sub>O<sub>3</sub>) Wheel

Finishing process of sapphire wafer is meeting huge challenge to fulfill the strict requirement of high surface quality in semiconductor industry. Fixed abrasive process, although can guarantee the profile accuracy, leaves damaged layer on the surface or subsurface of sapphire wafer. Chemical mechanical polishing (CMP) is famous for providing great surface roughness, however, sacrifices surface geometrical accuracy. Therefore, a new chromium oxide (Cr2O3) sapphire grinding wheel based on chemical mechanical grinding (CMG) principle has been developed and its performance has also been put into examination. The experiment result has demonstrated that Cr2O3 possesses an outstanding potential in terms of a high material removal rate of sapphire wafer, meanwhile, largely reduces surface roughness from about 150nm to below 10nm in 1 hour. In addition, the design of experiment (DOE) has also been carried out to study the effect of influencing factors towards ultimate surface roughness of sapphire wafer. It reveals that the revolution speed of sapphire wafer bears twice greater influence towards surface roughness than the revolution speed of grinding wheel.

Effect of Citric Acid in Chemical Mechanical Polishing (CMP) for Lithium Tantalate (LiTaO<sub>3</sub>) Wafer

Lithium tantalate (LiTaO3) has piezoelectric, electro-optical and nonlinear optical characteristics, and a wide transparency range going from ultraviolet to infrared. It is desirable that LiTaO3 wafer was a smooth surface in order to function with good quality. Chemical mechanical polishing (CMP) has been used to planarize integrated circuits (ICs) or obtain a high surface quality of the substrates. This paper investigates the effect of citric acid as an additive in the slurry for LiTaO3 CMP. The roughness of the wafers was measured by an atomic force microscopy (AFM, XE-100) after polishing. The slurry, which contains citric acid as an additive, has a higher material removal rate and friction force than a slurry without an additive. After polishing, the surface roughness of the LiTaO3 wafer can be reduced down to 1.7Å of Ra.

Force Modeling and Control of SiC Monocrystal Wafer Processing

Wire saws with fixed diamond abrasive are often used to cut hard and brittle materials owning to the wire saw's narrow kerf, low cutting force, and minimal material waste. Typically, the cutting force changes during the operation since the part diameter and the contact length between the wire saw and part (i.e., contact length) continuously change, even if the process parameters (i.e., wire saw velocity, part feed rate, part rotation speed, and wire saw tension) are fixed, leading to wire saw breakage, wafer collapse, and inferior surface roughness. This study addresses this issue by regulating the force via feedback control. The most significant process parameter affecting the normal force, namely, part feed rate, is taken as the control variable. A system identification routine is used to obtain the transfer function relating the normal force and commanded part feed rate and the model parameters are identified online. An adaptive force controller is designed, and simulation and experimental studies for SiC monocrystal wafer wire saw machining are conducted. The results show the dynamic model well characterizes the normal force generated when wire saw machining SiC monocrystal, and the adaptive controller can effectively track various normal reference force trajectories (i.e., constants, ramps, and sine waves). The experimental results demonstrate that the wire saw machining process with adaptive force control can improve the cutting productivity and significantly decrease wafer surface roughness as compared to the cutting process with a constant part feed rate.

The Effect of Etchant Concentration and Temperature on Surface Finish of Silicon Wafer Thinning

Fabrication of silicon (Si) wafer microfilters via focus ion beam (FIB) sputtering (milling/drilling) is planned. However, due to limitations of FIB sputtering, the wafer has to be initially thinned to a certain thickness to ensure that micron-scale through holes can be successfully manufactured. This paper reports on thinning of a silicon wafer via wet chemical etching using 15, 20, and 25% w/w potassium hydroxide (KOH) at 3 different etchant temperatures (80oC, 90oC, and 100oC). The target is to achieve 100 μm with the lowest time taken and wafer surface roughness after etching. From the experiments conducted, it was determined that KOH solution at 15% w/w concentration at 100oC produced the best result with an etch rate of 5.43 μm/min, surface roughness (Ra) of 0.12μm and thickness of 123.00μm.

Impact of Texture Roughness on the Front-Side Metallization of Stencil-Printed Silicon Solar Cells

Realizing narrow contact fingers with low lateral resistance is a major goal for the front-side metallization of silicon solar cells. The formation of screen- or stencil-printed contact fingers is governed by a variety of influencing factors. One of these factors is the surface roughness of the textured silicon wafer. However, only a few investigations have been carried out to investigate this impact in detail. In this study, the influence of arithmetical mean roughness $R_{{\rm a}}$ of four differently textured wafer surfaces on contact finger geometry and lateral finger resistance, as well as optical and electrical losses, has been investigated. It will be shown that texture roughness has a considerable impact on the properties of the front-side grid. Narrower contact fingers could be realized on the smoothest texture, leading to a current density gain of $\Delta j_{{\rm sc}} = +0.27$ mA/cm2. On the other hand, increasing texture roughness has affected the amount of transferred paste and, thus, has led to a lower lateral finger resistance R L. Thus, contact fingers on the roughest texture have benefited from a fill factor gain of Δ FF = +0.24 %abs. A sensitivity analysis of both impacts has shown that the current density gain has overcompensated the fill factor loss. Thus, textures with a small roughness are beneficial with respect to the formation and electrical properties of stencil-printed front-side grids.

The Influence of Wafer Cleaning Process on the Silicon Surface Roughness

The cleaning process of the silicon wafer becomes one of the most important procedures in semiconductor fabrication. It is acknowledged to remove the contamination on the wafer surface as well as to promote an acceptable surface roughness, prior to performing various deposition methods. The wafer cleaning process which based on hot alkaline and acidic solutions is known as the RCA cleaning. The RCA is still the most important wafer cleaning method used in wafer fabrication industry. In this paper, the effects of various cleaning procedure to the silicon wafer surface roughness are measured using AFM. Subsequently, an optimum cleaning recipe is discussed and proposed.

Experimental investigation into Ball end Magnetorheological Finishing of silicon

Ball end Magnetorheological Finishing (BEMRF) is a novel finishing process employed in the finishing of 2D and 3D surfaces. The magnetorheological effect imparted by the magnetic particles introduced through water or other carrier medium governs the finishing action of BEMRF. Abrasive and carrier medium play a vital role in the surface quality of the silicon material exposed to BEMRF process. In the present study, deionized water was used as a carrier medium while cerium oxide acted as an abrasive to finish the silicon wafer. An experimental study through statistical design of experiments were employed to predict the effect of process parameters such as core rotational speed, working gap, and magnetizing current on a percentage reduction in surface roughness of silicon wafer in BEMRF process. Individual effect on surface roughness values in terms of arithmetical mean roughness (Ra) was studied by applying ANOVA. The maximum contribution is made by the working gap on the surface finish was found to be the most critical aspect. Coming next was the magnetizing current while the last contribution was provided by the core rotational speed.

Time-varying wetting behavior on copper wafer treated by wet-etching

The wet cleaning process in semiconductor fabrication often involves the immersion of the copper wafer into etching solutions and thereby its surface properties are significantly altered. The wetting behavior of a copper film deposited on silicon wafer is investigated after a short dip in various etching solutions. The etchants include glacial acetic acid and dilute solutions of nitric acid, hydrofluoric acid, and tetramethylammonium hydroxide. It was found that in most cases a thin oxide layer still remains on the surface of as-received Cu wafers when they are subject to etching treatments. However, a pure Cu wafer can be obtained by the glacial acetic acid treatment and its water contact angle (CA) is about 45°. As the pure Cu wafer is placed in the ambient condition, the oxide thickness grows rapidly to the range of 10–20Å within 3h and the CA on the hydrophilic surface also rises. In the vacuum, it is surprising to find that the CA and surface roughness of the pure Cu wafer can grow significantly. These interesting results may be attributed to the rearrangement of surface Cu atoms to reduce the surface free energy.

Research on Surface Roughness of Acid Etched Silicon Wafers

With the development of power electronic devices, the market demand for acid etched wafers of monocrystalline silicon, which has good surface properties and minimum surface roughness, increases rapidly. But there has been rarely report about the impact of acid etching process on the wafer surface roughness. This paper studied the surface roughness of the wafer, which was etched by mixture of HNO3, HF and HAC. The results showed that the surface roughness became smaller with the increase of wafer remove amount, while the roughness became worse with the service life extension of the acid; however, fluid infusion discharge method could be adopted in the etching process so that the etching acid system could achieve a relatively balanced state and wafer roughness became stabilized. The process mechanism was studied and analyzed in this investigation.

金刚石线锯切割多晶硅片的气相刻蚀制绒研究

Vapor Etching(VE)was used to etch diamond wire sawn mc-silicon wafers.The vapor was generated from heating the acid mixture solution of HF-HNO3 in the volume ratio of 1:3(the total volume of the solution is 400mL)at 90 ℃.The results showed that etching for 15 minutes,saw marks can be removed and lots of small corrosion pits which appeared in big corrosion pits were densely covered with silicon wafer surface,the average size of the corrosion pits was about 1μm,while that by wet acid etch was over 10μm.The wafer surface roughness with VE method is actually 3times higher than that with traditional wet acid etching method.The effect of VE is obvious and the reflectivity is low to12.11%.

An Investigation on Two Types of Crystalline Micro-diamond Film Coated Tools Lapping with Sapphire Wafer

Two types of micron-diamond films were prepared on YG6 substrate by hot filament chemical vapor deposition(HFCVD) method. Morphology and orientation of crystalline growth were evaluated by SEM and XRD. Diamond film coated tools and sapphire wafer’ surface before and after lapping experiment were contrasted. The results indicated that a significant change in Raman spectrum of two types of micron-diamond film appeared after lapping. The two types of micron- diamond film’s graphitization were all obviously. The SMDF tool’s value of friction coefficient was larger than the FMDF’s. The surface roughness of sapphire wafer lapped by FMDF was lower than by SMDF. Compared two kinds of micron diamond film, FMCD's lapping effect was better.

Silicon Solar Wafers: Quality Control and Improving the Mechanical Properties

Additionally to the electrical properties of silicon solar wafers and cells, the mechanical properties (especially strength) must also need to be scrutinized investigated. This paper describes several aspects regarding silicon wafer crystal structure, saw-damage removal and surface roughness parameters in relation to mechanical strength. The results may be used to increase production yields, which ultimately leads to reduced cell costs.

Process study on large-size silicon wafer grinding by using a small-diameter wheel

Silicon (Si) is a fundamental material in the semiconductor industry. The advancement of semiconductor devices have offered convenience and comfort to our life. In order to raise productivity and economic efficiency, the semiconductor industry keeps looking for use of larger size Si wafers. The next generation wafer is expected to be sized as large as 450 mm in diameter. Many wafering processes including lapping, grinding and polishing have been studied and grinding technology stands out as the most promising process for large-size Si wafer manufacturing. In the current in-feed grinding scheme adopted for Si wafers, the wheel diameter used is generally equal to or larger than the wafer diameter. In turn, larger diameter wheels require larger size machine tools and production lines, which lead to increase in manufacturing costs. In this paper, both experiment and kinematical analysis have been carried out to investigate the feasibility of using small diameter grinding wheels to grind large size Si wafers, mainly focusing on the effects of wheel diameter on wafer geometry and surface roughness. The results show that both wheels generated a central convex profile on the wafer and the small wheel achieved a slightly better flatness than the large wheel. The surface roughness were similar one to another for most area of the wafer except the fringe around its edge. All these experimental results were predicable by the kinematic model established in this paper. Particularly, the kinematic analysis found that the cutting path made by small wheel with diameter equaling to the wafer radius was parallel each other at the fringe around wafer edge, which directly worsened the surface roughness.

Effective cleaning process and its influence on surface roughness in anodic bonding for semiconductor device packaging

Wafer cleanliness and surface roughness play a paramount role in an anodic bonding process. Impurities and the roughness on the wafer surface result in unbonded areas which lead to fringes and Newton׳s rings. With an augment in surface roughness, lesser area will be in stroke thus making more pressure and voltage to be applied onto the wafers for better bonding. Eventually it became mandatory to choose the best cleaning process for the bonding technology that can substantially reduce the impurities and surface roughness. In this paper, we investigate the bonding of silicon/oxidized silicon on Pyrex (CORNING 7740) glass with respect to surface roughness and cleanliness of the wafers by performing three renowned cleaning processes such as degreasing, piranha, RCA 1& 2 (SC‐Standard Cleaning 1 and 2) and found that RCA compromises the best between the roughness and cleanliness. Studies were also extended to find out the effects of applied voltage and load on the bonded surface. It was observed for samples cleaned with RCA, an increase of 45% in maximum current and decrease of 75% in total bonding time with the applied load and voltage among all the cleaning techniques used. Three dimensional structures for pressure sensor application were successfully bonded by selecting the appropriate load and cleaning process. Atomic force microscopy analysis was done to investigate the surface roughness on silicon/oxidized silicon and Pyrex glass for different cleaning processes. Scanning electron microscopy and optical imaging were performed on the interface for the surface integrity of the bonded samples.

Evaluation of planarization performance for a novel alkaline copper slurry under a low abrasive concentration

A novel alkaline copper slurry that possesses a relatively high planarization performance is investigated under a low abrasive concentration. Based on the action mechanism of CMP, the feasibility of using one type of slurry in copper bulk elimination process and residual copper elimination process, with different process parameters, was analyzed. In addition, we investigated the regular change of abrasive concentration effect on copper and tantalum removal rate and within wafer non-uniformity (WIWNU) in CMP process. When the abrasive concentration is 3 wt%, in bulk elimination process, the copper removal rate achieves 6125 Å/min, while WIWNU is 3.5%, simultaneously. In residual copper elimination process, the copper removal rate is approximately 2700 Å/min, while WIWNU is 2.8%. Nevertheless, the tantalum removal rate is 0 Å/min, which indicates that barrier layer isn't eliminated in residual copper elimination process. The planarization experimental results show that an excellent planarization performance is obtained with a relatively high copper removal rate in bulk elimination process. Meanwhile, after residual copper elimination process, the dishing value increased inconspicuously, in a controllable range, and the wafer surface roughness is only 0.326 nm (sq < 1 nm) after polishing. By comparison, the planarization performance and surface quality of alkaline slurry show almost no major differences with two kinds of commercial acid slurries after polishing. All experimental results are conducive to research and improvement of alkaline slurry in the future.