Wafer Stack Research Articles

Ultrafine Pitch (6 $\mu\hbox{m}$) of Recessed and Bonded Cu–Cu Interconnects by Three-Dimensional Wafer Stacking

In this letter, an evolution of high-density (>; 106 cm-2) bonded Cu-Cu interconnects of 6-μm pitch is successfully demonstrated using wafer-on-wafer thermocompression bonding. Cu sealing frame with excellent hermeticity is integrated to the bonded structures to promote bond reliability. Additionally, temporary passivation of Cu surface using self-assembled monolayer enhances the resistance against oxidation, which, in turn, enables moderately low-temperature bonding process at 300°C. Finally, thermal cycling test confirms the thermal stability of the 6-μm-pitch Cu-Cu daisy chain structure up to 1000 cycles. This work opens up new opportunity for wafer-level integration of bumpless Cu-Cu bonding to enable future high-bandwidth 3-D integrated circuit applications.

Design of Test Structures for the Characterization of Thermal–Mechanical Stress in 3D-Stacked IC

In this paper, we present test structures and measurement techniques that enable the extraction of the significance of the thermal–mechanical stress in 3D-stacked integrated circuit technology. Heaters and integrated diodes have been used to determine the impact of hotspots in 3-D systems. The results obtained showed that in 3-D case, the peak temperature of a hotspot is three times higher compared to a traditional 2-D system. For the characterization of through silicon vias (TSVs)-induced stress and its impact on analog metal-oxide semiconductor (MOS) devices, a 10-bit current steering digital-to-analog converter (DAC) test structure is utilized. The DAC has been optimized to detect ion changes down to 0.5% due to TSV proximity, TSV orientation, thermal hotspots, and wafer thinning or stacking process. The results obtained from stand-alone short-channel MOS devices and the DAC structure clearly indicate the impact of TSV proximity and TSV orientation on the carrier mobility of nearby transistors.

Fabrication and Challenges of Cu-to-Cu Wafer Bonding

The demand for 3D wafer level integration has been increasing significantly. Although many technical challenges of wafer stacking are still remaining, wafer stacking is a key technology for 3D integration due to a high volume manufacturing, smaller package size, low cost, and no need for known good die. Among several new process techniques Cu-to-Cu wafer bonding is the key process to be optimized for the high density and high performance IC manufacturing. In this study two main challenges for Cu-to-Cu wafer bonding were evaluated: misalignment and bond quality of bonded wafers. It is demonstrated that the misalignment in a bonded wafer was mainly due to a physical movement of spacer removal step and the bond quality was significantly dependent on Cu bump dishing and oxide erosion by Cu CMP.

3D Wafer Stacking via Bonding of Recessed Cu Damascene Structures

not Available.

Three-Dimensional Wafer Stacking Using Cu–Cu Bonding for Simultaneous Formation of Electrical, Mechanical, and Hermetic Bonds

Wafer-on-wafer stacking is demonstrated successfully using bumpless Cu-Cu bonding for the simultaneous formation of electrical connection, mechanical support, and hermetic frame for 3-D IC application. The ohmic behavior of the Cu-Cu bond is verified. A daisy chain of at least 44 000 contacts at a 15-μm pitch is connected successfully and sustains thermal cycling. Postbonding delamination is found to be strongly affected by the wafer curvature and bond strength. The Cu-Cu hermetic seal ring shows a helium leak rate more than ten times lower than the reject limit (5 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-8</sup> atm · cm/s based on MIL-STD-883E standard) without underfill. This provides a robust IC-to-IC connection density of 4.4 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> , suitable for future wafer-level 3-D integration.

Advanced Stepper Through-Silicon Alignment (TSA) Evaluation and Overlay of Distorted Bonded Wafer Stacks

Canon Litho Products support Vertical Lithography challenges required by TSV and advanced packaging applications that support “More-than-Moore” advancements. Vertical Lithography challenges include accurately performing backside, infrared alignment to distorted bonded-wafer grids and imaging through thick resist films. This paper will provide examples illustrating severe wafer distortion that can be experienced after wafer thinning and the impact of overlay and imaging control. This paper will also introduce Canon stepper features that are designed to address Vertical Lithography challenges including the Canon Through-Silicon Alignment (TSA) System and advanced Projection Lens. Grid distortion characterization data and stepper compensation results are presented to illustrate Canon stepper technology performance under severe process conditions.

Room Temperature Debonding - An Enabling Technology for TSV and 3D Integration

Thin wafer processing is a critical technology for TSV manufacturing and 3D integration. Thin wafer processing allows to reduce the aspect ratio of the vias, thereby reducing the total processing cost and enables ultra-thin packages for handheld applications. Temporary bonding to a rigid support carrier and debonding after backside processing have been used for thin wafer handling/processing for many years. However, so far all the debonding methods imposed severe limitations on the manufacturability. For light induced debonding the carrier had to be transparent and for solvent based debonding the carrier had to be perforated. For thermally induced debonding, “slide-off debonding” the debonding temperature had to be below the reflow temperature of the solder bumps, which limited the maximal process temperature of the adhesive. In this paper we describe a new debonding method at room temperature. This new technology decouples the debonding process from the adhesive properties, which creates a de facto material independent debonding standard. As the debonding process does not rely on the adhesive properties a major boundary for adhesive engineering has been removed. The debonding method is compatible with bumps or pillars in the bond interface as well as on the backside of the wafer stack. No force is applied on the bumps during debonding which results in very high yields.

Brewster’s angle silicon wafer terahertz linear polarizer

We present a new cost-effective terahertz linear polarizer made from a stack of silicon wafers at Brewster's angle, andevaluate its performances. We show that this polarizer is wide-band, has a high extinction ratio (> 6 × 10(3)) and very small insertion losses (< 1%). We provide measurements of the temporal waveforms after linearly polarizing the THz beam and show that there is no distortion of the pulse. We compare its performances with a commercial wire-grid polarizer, and show that the Brewster's angle polarizer can conveniently be used to control the power of a terahertz beam.

Stress analysis of stacked Si wafer in 3D WLP

In 3D wafer-stacking technology, one of the major manufacturing issues is wafer warpage because it causes process and product failures, such as delamination, cracking, mechanical stresses, and even electrical failure. In this study, the wafer warpage and local strain of thinned Si wafers in a wafer stack were investigated. A blanket Cu film was deposited on a Si wafer by a sputtering process. Two Cu deposited wafers were bonded by a thermo-compression method, and a stacked wafer was thinned down to 30 μm. The three wafers were then stacked on a Si wafer substrate. The wafer warpage and local strain of each stacked Si wafer were measured by film-stress measurement and the convergent-beam electron diffraction technique of transmission electron microscopy, respectively. An emphasis was placed on the effects of wafer stacking by Cu bonding and Si thinning on stress development in a thinned Si wafer. As the number of wafers in a stack increased, wafer warpage became severe, and the local strain in thinned Si wafers near the Si/Cu interface was increased.

Vertical junction Si cells for concentrating photovoltaics

ABSTRACTVertical junction Si cell has shown a potential to operate at high concentrations, mainly the result of reduced series resistance losses due to its low‐current/high‐voltage design, but tests and analyses have so far only shown a modest efficiency of about 20%. We perform a comprehensive optimization study and show that the conversion efficiency of vertical multi‐junction (VMJ) cells can be significantly higher, close to 30% at concentrations of 1000 and higher. Reaching this efficiency requires junction dimensions that are significantly smaller than previous VMJ cells. This may require a different approach in the fabrication process, possibly by using a monolithic method rather than the wafer stacking approach. We also show that increased photoconductivity, which is usually negligible in conventional cells, produces a significant reduction in series resistance at high concentrations making it a significant contributor to the outstanding performance of the VMJ cell at high concentration. Copyright © 2011 John Wiley &amp; Sons, Ltd.

Wafer-level bonding and direct electrical interconnection of stacked 3D MEMS by a hybrid low temperature process

The presented fabrication technology enables the direct integration of electrical interconnects during low temperature wafer bonding of stacked 3D MEMS and wafer-level packaging. The low temperature fabrication process is based on hydrophilic direct bonding of plasma activated Si/SiO2 surfaces and the simultaneous interconnection of two metallization layers by eutectic bonding of ultra-thin AuSn connects. This hybrid wafer-level bonding and interconnection technology allows for the integration of metal interconnects and multiple materials in stacked MEMS devices. The process flow is successfully validated by fabricating test structures made out of a two wafer stack and featuring multiple ohmic electrical interconnects.

Low Temperature Bonding with Thin Wafers for 3D Integration

The ITRS roadmap for high-density TSV interconnects specifies maximum layer thicknesses of 5-15 µm in 2013 with a sub-micron layer-to-layer alignment accuracy. For 3D chip stacks with multiple layers it is not only necessary to handle and process such thin layers, but later on these thin layers have to be stacked and bonded. When it comes to wafer bonding for high-density TSV integration, most efforts have been given to developing Cu-Cu thermo-compression bonding and direct oxide bonding. Stacking of thin wafers can be performed either after the thin wafer is debonded or while the thin wafer is still bonded onto a carrier wafer. Bonding of the thin wafer while still mounted to the carrier wafer allows comfortable and safe wafer handling, but adds some complexity to the wafer bonding process.

13nm gate Intentional Defect Array (IDA) wafer patterning by e-beam lithography for defect metrology evaluation

Fabricating and inspecting wafers with defects intentionally created at known locations enables a quantitative and repeatable methodology to assess the performance of in-line defect metrology tools with regard to ITRS requirements. With each successive design node, in-line defect inspection technology becomes more challenging and there are significant concerns about the capability to support 2× and 1× technology nodes. In this paper we report progress at the College of Nanoscale Science and Engineering (CNSE) in Albany, New York, to print and process advanced defect metrology test structures intended to represent a 13nm gate length. The ISMI 13nm gate Intentional Defect Array (IDA) has lithographic defects in known locations with sizes varying from 25% to 400% of the corresponding 32nm node, resulting in defect sizes ranging from 8 to 128nm. The film stack consists of 30nm TEOS hard mask, 60nm polysilicon, 35nm TiN and 2nm HfO2 on top of silicon. The patterns are first printed (at 1×) on a 300mm wafer using a Vistec VB300 electron beam lithography tool with a high resolution HSQ resist (commercially known as Dow Corning XR-1541). The features are subsequently etched to transfer the pat- tern from the resist onto the wafer stack. The resulting IDA wafers are intended to help ISMI engineers investigate next generation metrology techniques and identify solutions for future technology nodes.

Wafer warpage analysis of stacked wafers for 3D integration

The demand for wafer stacking technology has been increasing significantly. Although many technical challenges of wafer stacking have improved greatly, there are still many processing issues to be resolved. One of them is wafer warpage since it causes process and product failures such as delamination, cracking, mechanical stresses, and even electrical failure. In this study the warpage of multi-stacked wafers has been evaluated. Three Si wafers have been stacked on a Si substrate using a thermo-compression Cu bonding. Each wafer stack was ground down to ∼30 μm and the thickness of the thinned Si wafer and wafer curvature were measured by FTIR (Fourier Transform Infrared Spectrometer) and FSM (Film-Stress Measurement), respectively. Wafer curvature becomes severe as the number of wafers in a stack increases, but the increment of wafer bow is reduced as the number of stack increases. The experimental results were also compared with the analytical model.

Stacking of Known Good Rebuilt Wafers without TSV - Industrial Applications

The 3-D interconnection started at 3D PLUS in 1996 and led to the stacking of nearly all types of analogical and logical components, sensors, MEMS, etc for the Hi-Rel field (Space, Defence, Medical, Industrial). This technology is extremely robust (−130 °C +175 °C, 40000g), and is fully qualified by all worldwide most important Space Agencies, for Defence applications and Harsh environment. A technological break started in 2002 ; it consisted in another 20 to 30 reduction factor of the weight and volume of these 3-D modules. The Z pitch is 100 μm and the X Y size is given by the size of the larger die plus 100 μm of polymer around it. This is a stacked of Known Good Rebuilt Wafer of full wafer level technique. The dice are received in wafers and following operations are carried out :- Pick, flip and place of the good dice on a “sticking skin”- Moulding of the whole of this « pseudo wafer » in order to obtain what we call a « Known Good Rebuilt Wafer (KGRW) ». These two first steps are already developed by Freescale (RCP technique up to 300mm), then Infineon and Nanium (ex Infineon/Quimoda) and now about ten companies are developing this 2-D approach:- Stacking and gluing of KGRW 1, 2, 3..., n, by means of an adhesive film- Dicing of these stacked rebuilt wafers by techniques identical to the dicing of standard wafers- Metallization of the dicing streets with nickel + gold by electroless chemical plating identical to the UBM plating technique- Direct laser patterning by laser with our edge connection technique up to 100 μm pitch. Below this pitch, the Thru Polymer Via (TPV) are made through the stacked wafers. The equivalent pitch will be 20 μm. it can be noticed that the shielding can be made on the dicing street.- Electrical test at the stacked wafer level- Singulation This approach allows to use standard dice without any modification. It is multi sources and the stacking of the good rebuilt wafers allows to obtain an excellent yield. A development agreement has been signed with a semiconductors manufacturer. Smart card application- A development is in progress with the most worldwide important manufacturer of smart cards in order to integrate 5 levels of dice within a cavity of 550 μm inside the 800 μm SIM card. Medical applications will be presented:- Micro modulator with 5 ASICs within a 3 mm diameter tube,- Prototypes for the major US pacemaker manufacturer (Medtronic) and one European pacemaker manufacturer (Sorin/Ela Medical). A full pacemaker module of 0,5 cm3 (16 times smaller than the standard pacemaker: 8 cm3) will be shown- Micro camera for Hard X-Ray for Philips Medical (DE). Industrial applications- Abandoned sensors for Airbus and industrial areas. This « full wafer level » approach will allow to build System in Package (SiP) or “Abandoned Sensors” at very low costs, since the process uses mainly the steps of wafers building; the “panelization” allows to be in parallel processing from A to Z steps. Moreover, the use of Known Good Rebuilt Wafer like the RCP allows to stack Good wafer at the reverse what is impossible with the wafer to wafer approach.

300mm Wafer-Level Image Sensor Packaging

The image sensor market is still showing s tremendous market growth due to applications in consumer electronics, medical, automotive and communication. For a lot of new applications the image sensor packaging is in fact the enabling key technology. The introduction of wafer level packaging a couple of years ago allowed the cost reduction necessary for high volume consumer electronics. Innovative packaging concepts with TSVs and thin dies enable unmatched form factor. Currently scaling image sensor manufacturing and packaging to 300mm is the next big step forward in cost reduction. Wafer level image sensor packaging requires capping of the sensor wafer with a glass wafer. This heterogeneous integration of silicon and glass results in a variety of challenges like thermal expansion mismatch and bow and warp of the wafer stack. In this paper Tessera's OptiML Micro Via Pad technology for image sensors will be described with a special emphasis on equipment and process technology. Wafer encapsulation, via formation, electrical routing, passivation and solder bumping will be discussed.

New solid state lens for reflective neutron focusing

We have simulated, built and tested a neutron solid state lens based on a modified bender model. The device is 140mm long and has a focus at a distance of 31mm behind the end of the lens. It is made of two stacks of 150μm thick silicon wafers in an aluminum bender with a 20×30mm2 entrance window. The wafers are coated with m=2Ni–Ti supermirrors and the lens can thus accept the full divergence of a guide with the same wall coating. Measurements were performed with neutrons of wavelength 0.5nm at the HZB. They showed in the focal line a FWHM of 2.4mm and a maximum intensity gain of a factor 5.6 when compared to the intensity at the same position without the lens.

Hybrid low temperature wafer bonding and direct electrical interconnection of 3D MEMS

The presented fabrication technology enables the direct integration of electrical interconnects during low temperature wafer bonding of 3D MEMS and wafer-level packaging. The fabrication process relies on wafer stacking by hydrophilic direct bonding of plasma activated Si/SiO2 surfaces and the simultaneous interconnection of two metallization layers by eutectic bonding of ultra-thin AuSn connects. This hybrid low temperature bonding and interconnection technology allows for the integration of metal interconnects and multiple materials in stacked MEMS devices. Further, the technology is fully compatible with waferlevel packaging approaches based on through silicon vias (TSV) or CMOS/MEMS integration. The process flow is successfully validated by fabricating test structures made out of a two wafer stack and featuring multiple ohmic electrical interconnects.

Stacking of Known Good Rebuilt Wafers without TSV - Applications to Memories and SiP

The 3-D interconnection started at 3D PLUS in 1996 and led to the stacking of nearly all types of analogical and logical components, sensors, MEMS, etc for the Hi-Rel field (Space, Defence, Medical, Industrial). This technology is extremely robust (−130°C +175°C, 40000g), and is fully qualified by all worldwide most important Space Agencies and for Defence applications. A technological break started in 2002 ; It consisted in another 20 to 30 reduction factor of the weight and volume of these 3-D modules.The Z pitch is 100μm and the X Y size is given by the size of the larger die plus 100μm of polymer around it. This is a stacked of Known Good Rebuilt Wafer of full wafer level technique. The dice are received in wafers and following operations are carried out :- Pick, flip and place of the good dice on a “sticking skin”- Moulding of the whole of this « pseudo wafer » in order to obtain what we call a « Known Good Rebuilt Wafer (KGRW) ». These two first steps are already developed by Infineon and mainly Freescale (RCP technique up to 300mm)- Stacking and gluing of KGRW 1, 2, 3…, n, by means of an adhesive film- Dicing of these stacked rebuilt wafers by techniques identical to the dicing of standard wafers- Metallization of the dicing streets with nickel + gold by electroless chemical plating identical to the UBM plating technique- Direct laser patterning by laser with our edge connection technique up to 100μm pitch. Below this pitch, the Thru Polymer Via (TPV) are made through the stacked wafers. The equivalent pitch will be 20μm. it can be noticed that the shielding can be made on the dicing street.- Electrical test at the stacked wafer level- Singulation of the 3D modules This approach allows using standard dice without any modification. It is multi sources and the stacking of the good rebuilt wafers allows to get an excellent yield. A development agreement has been signed with a semiconductors manufacturer. A development is in progress with the most worldwide important manufacturer of smart cards in order to integrate 5 levels of dice (including a MEMS) within a cavity of 550 μm inside the 800μm SIM card. Other applications with MEMS will be presented:- “Abandoned Sensors” for Heath Monitoring of the aircraft structure developed during the European Program: “e-Cubes” ,- Gyroscope with 6 MEMS,- Micro camera for endoscopy…- Medical applications with an important development made for 3 major pacemaker manufacturers. This « full wafer level » approach will allow to build System in Package (SiP) or “Abandoned Sensors” at very low costs, since the process uses mainly the steps of wafers building; the “panelization” allows to be in parallel processing from A to Z steps. Moreover, the use of Known Good Rebuilt Wafer like the RCP allows stacking Good wafer at the reverse what is impossible with the wafer to wafer approach.

Assessment of ultra-thin Si wafer thickness in 3D wafer stacking

3D integration with multi-stacked wafers is a promising option to enhance device performance and density beyond traditional device scaling limits. However, to bring wafer stacking into reality, there are many technological challenges to be resolved, and one of those is the problem of uniform Si wafer thinning. For multi-stacked devices, Si wafers must be drastically thinned down to less than 50 μm. Problems associated with such ultra-thin Si wafers range from basic wafer handling to difficulty in accurately assessing the thickness of the thinned wafer across the wafer. In this study, bonded wafer pairs have been prepared with different bonding materials, and the stacks were ground down to about 30 μm. The thickness of the ultra-thin wafers was measured by Fourier transform infrared spectrometry (FTIR) technique, and its stability based on bonding status as well as measuring issues will be discussed.