13nm gate Intentional Defect Array (IDA) wafer patterning by e-beam lithography for defect metrology evaluation

Abstract

Fabricating and inspecting wafers with defects intentionally created at known locations enables a quantitative and repeatable methodology to assess the performance of in-line defect metrology tools with regard to ITRS requirements. With each successive design node, in-line defect inspection technology becomes more challenging and there are significant concerns about the capability to support 2× and 1× technology nodes. In this paper we report progress at the College of Nanoscale Science and Engineering (CNSE) in Albany, New York, to print and process advanced defect metrology test structures intended to represent a 13nm gate length. The ISMI 13nm gate Intentional Defect Array (IDA) has lithographic defects in known locations with sizes varying from 25% to 400% of the corresponding 32nm node, resulting in defect sizes ranging from 8 to 128nm. The film stack consists of 30nm TEOS hard mask, 60nm polysilicon, 35nm TiN and 2nm HfO2 on top of silicon. The patterns are first printed (at 1×) on a 300mm wafer using a Vistec VB300 electron beam lithography tool with a high resolution HSQ resist (commercially known as Dow Corning XR-1541). The features are subsequently etched to transfer the pat- tern from the resist onto the wafer stack. The resulting IDA wafers are intended to help ISMI engineers investigate next generation metrology techniques and identify solutions for future technology nodes.