Stress analysis of stacked Si wafer in 3D WLP

Abstract

In 3D wafer-stacking technology, one of the major manufacturing issues is wafer warpage because it causes process and product failures, such as delamination, cracking, mechanical stresses, and even electrical failure. In this study, the wafer warpage and local strain of thinned Si wafers in a wafer stack were investigated. A blanket Cu film was deposited on a Si wafer by a sputtering process. Two Cu deposited wafers were bonded by a thermo-compression method, and a stacked wafer was thinned down to 30 μm. The three wafers were then stacked on a Si wafer substrate. The wafer warpage and local strain of each stacked Si wafer were measured by film-stress measurement and the convergent-beam electron diffraction technique of transmission electron microscopy, respectively. An emphasis was placed on the effects of wafer stacking by Cu bonding and Si thinning on stress development in a thinned Si wafer. As the number of wafers in a stack increased, wafer warpage became severe, and the local strain in thinned Si wafers near the Si/Cu interface was increased.