Wafer Scale Integration Research Articles

Wafer-Scale Integration of Graphene-based Electronic, Optoelectronic and Electroacoustic Devices

In virtue of its superior properties, the graphene-based device has enormous potential to be a supplement or an alternative to the conventional silicon-based device in varies applications. However, the functionality of the graphene devices is still limited due to the restriction of the high cost, the low efficiency and the low quality of the graphene growth and patterning techniques. We proposed a simple one-step laser scribing fabrication method to integrate wafer-scale high-performance graphene-based in-plane transistors, photodetectors, and loudspeakers. The in-plane graphene transistors have a large on/off ratio up to 5.34. And the graphene photodetector arrays were achieved with photo responsivity as high as 0.32 A/W. The graphene loudspeakers realize wide-band sound generation from 1 to 50 kHz. These results demonstrated that the laser scribed graphene could be used for wafer-scale integration of a variety of graphene-based electronic, optoelectronic and electroacoustic devices.

Graphene and Thin-Film Semiconductor Heterojunction Transistors Integrated on Wafer Scale for Low-Power Electronics

Graphene heterostructures in which graphene is combined with semiconductors or other layered 2D materials are of considerable interest, as a new class of electronic devices has been realized. Here we propose a technology platform based on graphene-thin-film-semiconductor-metal (GSM) junctions, which can be applied to large-scale and power-efficient electronics compatible with a variety of substrates. We demonstrate wafer-scale integration of vertical field-effect transistors (VFETs) based on graphene-In-Ga-Zn-O (IGZO)-metal asymmetric junctions on a transparent 150 × 150 mm(2) glass. In this system, a triangular energy barrier between the graphene and metal is designed by selecting a metal with a proper work function. We obtain a maximum current on/off ratio (Ion/Ioff) up to 10(6) with an average of 3010 over 2000 devices under ambient conditions. For low-power logic applications, an inverter that combines complementary n-type (IGZO) and p-type (Ge) devices is demonstrated to operate at a bias of only 0.5 V.

Electronic and photonic integrated circuits for fast data center optical circuit switches

This article surveys recent work in optical switching technologies and presents a fast optical circuit switch that intimately integrates the control electrics at the chip level using a novel wafer-scale heterogeneous integration technique.

InP-DHBT-on-BiCMOS Technology With $f_{T}/f_{\max}$ of 400/350 GHz for Heterogeneous Integrated Millimeter-Wave Sources

This paper presents a novel InP-SiGe BiCMOS technology using wafer-scale heterogeneous integration. The vertical stacking of the InP double heterojunction bipolar transistor (DHBT) circuitry directly on top of the BiCMOS wafer enables ultra-broadband interconnects with <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${&lt;}{0.2}~{\rm dB}$</tex></formula> insertion loss from 0–100 GHz. The <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$0.8\times 5~\mu{\rm m}^{2}$</tex></formula> InP DHBTs show <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$f_{T}/f_{\max}$</tex></formula> of 400/350 GHz with an output power of more than 26 mW at 96 GHz. These are record values for a heterogeneously integrated transistor on silicon. As a circuit example, a 164-GHz signal source is presented. It features a voltage-controlled oscillator in BiCMOS, which drives a doubler-amplifier chain in InP DHBT technology.

(Invited) Heterogeneous Integration of InP HBTs on CMOS: Leveraging and Providing Value to Conventional Silicon Technologies

Historically, compound semiconductors have enjoyed the benefit of material properties that lend themselves to high performance electron devices, but the ability to fabricate complex, high transistor count ICs is limited by the relative immaturity of the material system and small commercial market. Silicon based devices have made significant advances in device performance, but have not yet matched compound semiconductor device performance. However, a large commercial market has allowed the silicon system to mature and produce billion transistor count ICs in high volume. It would be advantageous to combine the merits of both compound semiconductors and silicon based CMOS/BiCMOS to enable a new class of high performance ICs. This work will review HRL's efforts in wafer scale integration of an advanced 250nm, 350GHz fT/fMAX InP DHBT technology with RF-CMOS technologies whose device proximity; heterogeneous interconnect density; and additional technology features both leverage and provide additional value to conventional silicon technologies.

Mixed pulses

Researchers from Eidgenössische Technische Hochschule Zürich (ETH Zürich) in Switzerland have achieved a record high average power for modelocked integrated external-cavity surface emitting laser (MIXSEL) oscillators. After absorber optimisation, structure design and thermal improvements, their laser, presented in this issue of Electronics Letters, produced 2.4 W at 10 GHz in 17 ps pulses. The MIXSEL chip is also simple with only two components, and has the potential for full wafer scale integration of the laser cavity.

Wafer-scale integration of group III–V lasers on silicon using transfer printing of epitaxial layers

The realization of GaAs lasers on a silicon substrate using a print transfer process offers an alternative wafer-bonding technique for the hybrid integration of optoelectronics.

Selective Synthesis and Device Applications of Semiconducting Single-Walled Carbon Nanotubes Using Isopropyl Alcohol as Feedstock

The development of guided chemical vapor deposition (CVD) growth of single-walled carbon nanotubes provides a great platform for wafer-scale integration of aligned nanotubes into circuits and functional electronic systems. However, the coexistence of metallic and semiconducting nanotubes is still a major obstacle for the development of carbon-nanotube-based nanoelectronics. To address this problem, we have developed a method to obtain predominantly semiconducting nanotubes from direct CVD growth. By using isopropyl alcohol (IPA) as the carbon feedstock, a semiconducting nanotube purity of above 90% is achieved, which is unambiguously confirmed by both electrical and micro-Raman measurements. Mass spectrometric study was performed to elucidate the underlying chemical mechanism. Furthermore, high performance thin-film transistors with an on/off ratio above 10(4) and mobility up to 116 cm(2)/(V·s) have been achieved using the IPA-synthesized nanotube networks grown on silicon substrate. The method reported in this contribution is easy to operate and the results are highly reproducible. Therefore, such semiconducting predominated single-walled carbon nanotubes could serve as an important building block for future practical and scalable carbon nanotube electronics.

In-situ grown horizontal carbon nanotube membrane

We present the successful fabrication of horizontally grown and dense carbon nanotube (CNT) membranes in situ. A TiN/Al2O3/TiN stack is first patterned to be employed as a support for the CNT growth. Iron is then evaporated with a 45^o tilt angle on the stack's vertical sidewall as a catalyst material. With the use of a material selective chemical vapor deposition (CVD) growth process, dense and thin arrays of horizontally aligned CNTs are directly grown on site, from the Al2O3/Fe surface. This process enables for the wafer scale integration of dense CNT membranes as basic building blocks in devices such as micro-electromechanical systems (MEMS) for gas sensing applications. These CNT membranes, when contacted in between interdigitated electrodes over a third buried electrode, can be expected to show enhanced sensitivity for potential gas identification sensor systems due to their large detection surface and enhanced selectivity due to potential ''signature'' multiple readouts of target molecules interactions with the CNT membrane.

The fabrication of vertically aligned and periodically distributed carbon nanotube bundles and periodically porous carbon nanotube films through a combination of laser interference ablation and metal-catalyzed chemical vapor deposition

Scalable fabrication of carbon nanotube (CNT) bundles is essential to future advances in several applications. Here, we report on the development of a simple, two-step method for fabricating vertically aligned and periodically distributed CNT bundles and periodically porous CNT films at the sub-micron scale. The method involves laser interference ablation (LIA) of an iron film followed by CNT growth via iron-catalyzed chemical vapor deposition. CNT bundles with square widths ranging from 0.5 to 1.5 µm in width, and 50–200 µm in length, are grown atop the patterned catalyst over areas spanning 8 cm2. The CNT bundles exhibit a high degree of control over square width, orientation, uniformity, and periodicity. This simple scalable method of producing well-placed and oriented CNT bundles demonstrates a high application potential for wafer-scale integration of CNT structures into various device applications, including IC interconnects, field emitters, sensors, batteries, and optoelectronics, etc.

A combination of capillary and dielectrophoresis-driven assembly methods for wafer scale integration of carbon-nanotube-based nanocarpets

The wafer scale integration of carbon nanotubes (CNT) remains a challenge for electronic and electromechanical applications. We propose a novel CNT integration process relying on the combination of controlled capillary assembly and buried electrode dielectrophoresis (DEP). This process enables us to monitor the precise spatial localization of a high density of CNTs and their alignment in a pre-defined direction. Large arrays of independent and low resistivity (4.4 × 10−5 Ω m) interconnections were achieved using this hybrid assembly with double-walled carbon nanotubes (DWNT). Finally, arrays of suspended individual CNT carpets are realized and we demonstrate their potential use as functional devices by monitoring their resonance frequencies (ranging between 1.7 and 10.5 MHz) using a Fabry–Perot interferometer.

Integrated MEMS-Tunable VCSELs Using a Self-Aligned Reflow Process

A simple microelectromechanical systems technology for wafer-scale integration of tunable vertical-cavity surface-emitting lasers (VCSELs) is presented. The key element is a self-aligned reflow process to form photoresist droplets, which serve as sacrificial layer and preform for a curved micromirror. Using a 3-D electromagnetic model, the half-symmetric cavity is optimized for singlemode emission. The technology is demonstrated for electrically pumped, short-wavelength (850 nm) tunable VCSELs, but is transferable to other wavelengths and material systems. Fabricated devices with 10 μm large current aperture are singlemode and tunable over 24 nm. An improved high-speed design with reduced parasitic capacitance enables direct modulation with 3 dB-bandwidths up to 6 GHz and data transmission at 5 Gbit/s. Small signal analysis shows that the intrinsic parameters (resonance frequency and damping) are wavelength dependent through the differential gain.

Vertically stacked RF switches by wafer-scale three-dimensional integration

Vertically stacked RF switches implemented by wafer-scale three-dimensional (3D) integration of three completely fabricated silicon-on-insulator wafers are demonstrated. The individual switch performance was maintained through the 3D integration process while the signal path is shortened by vertical interconnects. The footprint of the switch can be shrunk in proportion to the number of tiers it is distributed between, demonstrating the potential of significant size reduction of multiple-throw switches commonly required in many applications.

Close to tiers

A new class of RF switches have been developed by MIT Lincoln Laboratory in the US. The single chip high-performance vertically stacked switches are based on a wafer-scale 3D integration technology, and have a footprint that is much smaller than in conventional 2D switches. The approach, which is fully compatible with the standard Si CMOS process, could also be used for other types of circuit such as amplifiers, signal processors and imagers.

Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking

This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.

Monolithic integration of Si nanowires with metallic electrodes: NEMS resonator and switch applications

The challenge of wafer-scale integration of silicon nanowires into microsystems is addressed by developing a fabrication approach that utilizes a combination of Bosch-process-based nanowire fabrication with surface micromachining and chemical–mechanical-polishing-based metal electrode/contact formation. Nanowires up to a length of 50 µm are achieved while retaining submicron nanowire-to-electrode gaps. The scalability of the technique is demonstrated through using no patterning method other than optical lithography on conventional SOI substrates. Structural integrity of double-clamped nanowires is evaluated through a three-point bending test, where good clamping quality and fracture strengths approaching the theoretical strength of the material are observed. Resulting devices are characterized in resonator and switch applications—two areas of interest for CMOS-compatible solutions—with all-electrical actuation and readout schemes. Improvements and tuning of obtained performance parameters such as resonance frequency, quality factor and pull-in voltage are simply a question of conventional design and process adjustments. Implications of the proposed technique are far-reaching including system-level integration of either single-nanowire devices within thick Si layers or nanowire arrays perpendicular to the plane of the substrate.

InxGa1-xAs Nanowires on Silicon: One-Dimensional Heterogeneous Epitaxy, Bandgap Engineering, and Photovoltaics

We report on the one-dimensional (1D) heteroepitaxial growth of In(x)Ga(1-x)As (x = 0.2-1) nanowires (NWs) on silicon (Si) substrates over almost the entire composition range using metalorganic chemical vapor deposition (MOCVD) without catalysts or masks. The epitaxial growth takes place spontaneously producing uniform, nontapered, high aspect ratio NW arrays with a density exceeding 1 × 10(8)/cm(2). NW diameter (∼30-250 nm) is inversely proportional to the lattice mismatch between In(x)Ga(1-x)As and Si (∼4-11%), and can be further tuned by MOCVD growth condition. Remarkably, no dislocations have been found in all composition In(x)Ga(1-x)As NWs, even though massive stacking faults and twin planes are present. Indium rich NWs show more zinc-blende and Ga-rich NWs exhibit dominantly wurtzite polytype, as confirmed by scanning transmission electron microscopy (STEM) and photoluminescence spectra. Solar cells fabricated using an n-type In(0.3)Ga(0.7)As NW array on a p-type Si(111) substrate with a ∼ 2.2% area coverage, operates at an open circuit voltage, V(oc), and a short circuit current density, J(sc), of 0.37 V and 12.9 mA/cm(2), respectively. This work represents the first systematic report on direct 1D heteroepitaxy of ternary In(x)Ga(1-x)As NWs on silicon substrate in a wide composition/bandgap range that can be used for wafer-scale monolithic heterogeneous integration for high performance photovoltaics.

Tensile-strained germanium-on-insulator substrate fabrication for silicon-compatible optoelectronics

We present a method to fabricate tensile-strained germanium-on-insulator (GOI) substrates using heteroepitaxy and layer transfer techniques. The motivation is to obtain a high-quality wafer-scale GOI platform suitable for silicon-compatible optoelectronic device fabrication. Crystal quality is assessed using X-Ray Diffraction (XRD) and Transmission Electron Microscopy. A biaxial tensile film strain of 0.16% is verified by XRD. Suitability for device manufacturing is demonstrated through fabrication and characterization of metal–semiconductor–metal photodetectors that exhibit photoresponse beyond 1.55 μm. The substrate fabrication process is compatible with complementary metal–oxide–semiconductor manufacturing and represents a potential route to wafer-scale integration of silicon-compatible optoelectronics.

Integrated MEMS-tunable VCSELs with high modulation bandwidth

The modulation bandwidth of micromachined tunable VCSELs is typically limited by the parasitic capacitance associated with the large mesa platform for the movable mirror. Presented is a simple technology for wafer-scale integration of tunable VCSELs with low mesa capacitance and high modulation bandwidth. Small signal measurements show a 3dB bandwidth of up to 6 GHz over a tuning range of 18 nm. Digital modulation is demonstrated with error-free data transmission at 5 Gbit/s and eye diagrams at 10 Gbit/s.

Single-walled carbon nanotube microsensors for nerve agent simulant detection

In this work we report on the fabrication and characterization of single-walled carbon nanotubes (SWCNTs) as sensitive layers for the detection of simulants of Chemical Warfare Agents (CWAs). The microsensor fabrication has been achieved after the wafer scale integration of the selective synthesis of SWCNTs as sensitive layer. Their electrical characterization has been carried out by measuring the resistance changes of the SWCNT networks when interacting with very low concentrations of CWA simulants such as dimethyl methyl phosphonate (DMMP), dipropylene glycol methyl ether (DPGME) and dimethylacetamide (DMA) at low temperatures, which are simulants of Sarin, Nitrogen Mustard and Distilled Mustard, respectively.