Wafer Scale Integration Research Articles

Novel Multi-State QDC-QDG FETs and Gate All Around (GAA) FETs for Integrated Logic and QD-NVRAMs

This paper presents experimental I-V characteristics of a QDC-QDG FET that exhibited 5-states and has the potential to introduce additional states (e.g. 8) by utilizing Ge QDSL mini-energy sub-bands. Mini-energy bands are formed in an asymmetric Si quantum dot channel (QDC) comprising of two silicon oxide cladded Si quantum dots (QDs), where the upper layer has a smaller core diameter and thicker upper oxide cladding serving as tunnel oxide. Quantum simulations are presented to show more states when additional two germanium oxide cladded Ge dots are added on top of Si QD layers in the gate region. This paper also proposes Gate all around (GAA) FETs, when integrated with nonvolatile random access memories (NVRAMs) that have the potential for wafer scale integration, similar to vertical NANDs. Novel Si and Ge Quantum-dot-based device configurations discussed in this paper open the pathway forward to implement hardware platform for emerging applications using low power consumption and smaller footprint.

Wafer-scale heterogeneous integration of self-powered lead-free metal halide UV photodetectors with ultrahigh stability and homogeneity

Large-scale growth and heterogeneous integration with existing semiconductors are the main obstacles to the application of metal halide perovskites in optoelectronics. Herein, a universal vacuum evaporation strategy is presented to prepare copper halide films with wafer-scale spatial homogeneity. Benefiting from the electric field manipulation method, the built-in electric fields are optimized and further boost the self-powered UV photodetecting performances of common wide-bandgap semiconductors by more than three orders of magnitude. Furthermore, with effective modulation of the interfacial charge dynamics, the as-fabricated GaN-substrate heterojunction photodetector demonstrates an ultrahigh on/off ratio exceeding 107, an impressive responsivity of up to 256 mA W–1, and a remarkable detectivity of 2.16 × 1013 Jones at 350 nm, 0 V bias. Additionally, the device exhibits an ultrafast response speed (tr/td = 716 ns/1.30 ms), an ultra-narrow photoresponse spectrum with an FWHM of 18 nm and outstanding continuous operational stability as well as long-term stability. Subsequently, a 372-pixel light-powered imaging sensor array with the coefficient of variation of photocurrents reducing to 5.20% is constructed, which demonstrates exceptional electrical homogeneity, operational reliability, and UV imaging capability. This strategy provides an efficient way for large-scale integration of metal halide perovskites with commercial semiconductors for miniature optoelectronic devices.

Large-area multilayer molybdenum disulfide for 2D memristors

Resistive random access memories (RRAMs) using two-dimensional (2D) materials have delivered comparable switching performance with CMOS devices. However, devices risk short problems because of their ultra-thin body, thus yielding poorly. In this study, we realize high-yield RRAMs thanks to the synthesis of uniform large-area multilayer molybdenum disulfide by thermally decomposing ammonium tetrathiomolybdate. This top-down method has advantages over mainstream chemical vapor deposition, in which layer-by-layer epitaxy is forbidden when surface energy elevates. The resulting film surface roughness is down to 93.8 pm, and its lateral size can be scaled up to wafer scale. A yield value higher than 90% was estimated by testing 8 × 8 RRAM arrays, reaching nearly 100% in isolated devices. These devices show low operation voltages (∼1V) with low cycle-to-cycle and device-to-device variations (∼12%). We also observed stable resistive switching of multilayer films prepared at 400 °C. The large-area synthesis of uniform multilayer films makes it more feasible to use 2D semiconductors in practical RRAM technology for wafer-scale integration.

Impurities and defects in 4H silicon carbide

The widespread use of 4H silicon carbide (4H-SiC) is just around the corner since high-power electronics based on 4H-SiC are increasingly fabricated to enable the low-carbon development of the world. Quantum technologies are also intensively explored by scrutinizing 4H-SiC as a platform for wafer-scale integration of semiconductor and quantum technologies. Given the importance of impurities and defects for any semiconductor, comprehensive and insightful understanding of impurities and defects in 4H-SiC is imperative. In this Perspective, we summarize recent experimental and theoretical advances in researches on impurities and defects in 4H-SiC after briefly reviewing the history of 4H-SiC. Impurity engineering and defect engineering for the realization of the full potential of 4H-SiC are also discussed. Challenges for the study on impurities and defects in 4H-SiC are finally outlined.

Wafer-scale heterogeneous integration of thin film lithium niobate on silicon-nitride photonic integrated circuits with low loss bonding interfaces.

Silicon nitride (Si3N4) is a versatile waveguide material platform for CMOS foundry-based photonic integrated circuits (PICs) with low loss and high-power handling. The range of applications enabled by this platform is significantly expanded with the addition of a material with large electro-optic and nonlinear coefficients such as lithium niobate. This work examines the heterogeneous integration of thin-film lithium-niobate (TFLN) on silicon-nitride PICs. Bonding approaches are evaluated based on the interface used (SiO2, Al2O3 and direct) to form hybrid waveguide structures. We demonstrate low losses in chip-scale bonded ring resonators of 0.4 dB/cm (intrinsic Q = 8.19 × 105). In addition, we are able to scale the process to demonstrate bonding of full 100-mm TFLN wafers to 200-mm Si3N4 PIC wafers with high layer transfer yield. This will enable future integration with foundry processing and process design kits (PDKs) for applications such as integrated microwave photonics and quantum photonics.

Wafer-scale and universal van der Waals metal semiconductor contact

Van der Waals (vdW) metallic contacts have been demonstrated as a promising approach to reduce the contact resistance and minimize the Fermi level pinning at the interface of two-dimensional (2D) semiconductors. However, only a limited number of metals can be mechanically peeled and laminated to fabricate vdW contacts, and the required manual transfer process is not scalable. Here, we report a wafer-scale and universal vdW metal integration strategy readily applicable to a wide range of metals and semiconductors. By utilizing a thermally decomposable polymer as the buffer layer, different metals were directly deposited without damaging the underlying 2D semiconductor channels. The polymer buffer could be dry-removed through thermal annealing. With this technique, various metals could be vdW integrated as the contact of 2D transistors, including Ag, Al, Ti, Cr, Ni, Cu, Co, Au, Pd. Finally, we demonstrate that this vdW integration strategy can be extended to bulk semiconductors with reduced Fermi level pinning effect.

Wafer-scale alignment and integration of micro-light-emitting diodes using engineered van der Waals forces

Wafer-scale alignment and integration of micro-light-emitting diodes using engineered van der Waals forces

Colloidal Ag2Se intraband quantum dots.

With the emergence of the Internet of Things, wearable electronics, and machine vision, the exponentially growing demands for miniaturization, energy efficiency, and cost-effectiveness have imposed critical requirements on the size, weight, power consumption and cost (SWaP-C) of infrared detectors. To meet this demand, new sensor technologies that can reduce the fabrication cost associated with semiconductor epitaxy and remove the stringent requirement for cryogenic cooling are under active investigation. In the technologically important spectral region of mid-wavelength infrared, intraband colloidal quantum dots are currently at the forefront of this endeavor, with wafer-scale monolithic integration and Auger suppression being the key material capabilities to minimize the sensor's SWaP-C. In this Feature Article, we provide a focused review on the development of sensors based on Ag2Se intraband colloidal quantum dots, a heavy metal-free colloidal nanomaterial that has merits for wide-scale adoption in consumer and industrial sectors.

Wafer-scale integration of GaAs/AlGaAs core-shell nanowires on silicon by the single process of self-catalyzed molecular beam epitaxy.

GaAs/AlGaAs core-shell nanowires, typically having 250 nm diameter and 6 μm length, were grown on 2-inch Si wafers by the single process of molecular beam epitaxy using constituent Ga-induced self-catalysed vapor-liquid-solid growth. The growth was carried out without specific pre-treatment such as film deposition, patterning, and etching. The outermost Al-rich AlGaAs shells form a native oxide surface protection layer, which provides efficient passivation with elongated carrier lifetime. The 2-inch Si substrate sample exhibits a dark-colored feature due to the light absorption of the nanowires where the reflectance in the visible wavelengths is less than 2%. Homogeneous and optically luminescent and adsorptive GaAs-related core-shell nanowires were prepared over the wafer, showing the prospect for large-volume III-V heterostructure devices available with this approach as complementary device technologies for integration with silicon.

A Detailed Analysis of Wafer Scale Integration and Multichip Modules

Hybrid integration of functional multichip layers and electronic devices has received a significant research interest from both industry and academia. While moving towards the end of Moore's law, the power consumption and device scaling remain as significant challenges, necessitating the development of beyond-multichip technologies to achieve high performance computing. While conventional techniques like wafer based bonding and pick-and-place can only partially address the aforementioned challenges, a variety of new multi-chip transfer and wafer scale circuit integration approaches have been developed. This review summarizes such wafer scale integration and neural networks based on multichip modules for many applications, such as flexible electronics, smart displays, and gaming. The proposed study has showcased a wide range of multi-chip modules, and the need for wafer scale integration with expanded functionalities. Finally, a detailed analysis on the advantages of the state-of-the-art techniques has been provided and the future research directions are discussed.

A Detailed Analysis of Wafer Scale Integration and Multichip Modules

Hybrid integration of functional multichip layers and electronic devices has received a significant research interest from both industry and academia. While moving towards the end of Moore's law, the power consumption and device scaling remain as significant challenges, necessitating the development of beyond-multichip technologies to achieve high performance computing. While conventional techniques like wafer based bonding and pick-and-place can only partially address the aforementioned challenges, a variety of new multi-chip transfer and wafer scale circuit integration approaches have been developed. This review summarizes such wafer scale integration and neural networks based on multichip modules for many applications, such as flexible electronics, smart displays, and gaming. The proposed study has showcased a wide range of multi-chip modules, and the need for wafer scale integration with expanded functionalities. Finally, a detailed analysis on the advantages of the state-of-the-art techniques has been provided and the future research directions are discussed.

Challenges for Nanoscale CMOS Logic Based on Two-Dimensional Materials.

For ultra-scaled technology nodes at channel lengths below 12 nm, two-dimensional (2D) materials are a potential replacement for silicon since even atomically thin 2D semiconductors can maintain sizable mobilities and provide enhanced gate control in a stacked channel nanosheet transistor geometry. While theoretical projections and available experimental prototypes indicate great potential for 2D field effect transistors (FETs), several major challenges must be solved to realize CMOS logic circuits based on 2D materials at the wafer scale. This review discusses the most critical issues and benchmarks against the targets outlined for the nm node in the International Roadmap for Devices and Systems scheduled for 2034. These issues are grouped into four areas; device scaling, the formation of low-resistive contacts to 2D semiconductors, gate stack design, and wafer-scale process integration. Here, we summarize recent developments in these areas and identify the most important future research questions which will have to be solved to allow for industrial adaptation of the 2D technology.

Silicon nitride stress-optic microresonator modulator for optical control applications.

Modulation-based control and locking of lasers, filters and other photonic components is a ubiquitous function across many applications that span the visible to infrared (IR), including atomic, molecular and optical (AMO), quantum sciences, fiber communications, metrology, and microwave photonics. Today, modulators used to realize these control functions consist of high-power bulk-optic components for tuning, sideband modulation, and phase and frequency shifting, while providing low optical insertion loss and operation from DC to 10s of MHz. In order to reduce the size, weight and cost of these applications and improve their scalability and reliability, modulation control functions need to be implemented in a low loss, wafer-scale CMOS-compatible photonic integration platform. The silicon nitride integration platform has been successful at realizing extremely low waveguide losses across the visible to infrared and components including high performance lasers, filters, resonators, stabilization cavities, and optical frequency combs. Yet, progress towards implementing low loss, low power modulators in the silicon nitride platform, while maintaining wafer-scale process compatibility has been limited. Here we report a significant advance in integration of a piezo-electric (PZT, lead zirconate titanate) actuated micro-ring modulation in a fully-planar, wafer-scale silicon nitride platform, that maintains low optical loss (0.03 dB/cm in a 625 µm resonator) at 1550 nm, with an order of magnitude increase in bandwidth (DC - 15 MHz 3-dB and DC - 25 MHz 6-dB) and order of magnitude lower power consumption of 20 nW improvement over prior PZT modulators. The modulator provides a >14 dB extinction ratio (ER) and 7.1 million quality-factor (Q) over the entire 4 GHz tuning range, a tuning efficiency of 162 MHz/V, and delivers the linearity required for control applications with 65.1 dB·Hz2/3 and 73.8 dB·Hz2/3 third-order intermodulation distortion (IMD3) spurious free dynamic range (SFDR) at 1 MHz and 10 MHz respectively. We demonstrate two control applications, laser stabilization in a Pound-Drever Hall (PDH) lock loop, reducing laser frequency noise by 40 dB, and as a laser carrier tracking filter. This PZT modulator design can be extended to the visible in the ultra-low loss silicon nitride platform with minor waveguide design changes. This integration of PZT modulation in the ultra-low loss silicon nitride waveguide platform enables modulator control functions in a wide range of visible to IR applications such as atomic and molecular transition locking for cooling, trapping and probing, controllable optical frequency combs, low-power external cavity tunable lasers, quantum computers, sensors and communications, atomic clocks, and tunable ultra-low linewidth lasers and ultra-low phase noise microwave synthesizers.

Hardware Implementation of a Brain Model on Wafer Scale Integration Technologies and Its Fault Tolerance

Hardware Implementation of a Brain Model on Wafer Scale Integration Technologies and Its Fault Tolerance

Formation of Q-carbon with wafer scale integration

We describe the formation of highly uniform Quenched-carbon (Q-carbon) layers by plasma-enhanced chemical vapor deposition (PECVD) followed by low-energy Ar+ ion bombardment to achieve wafer-scale integration of Q-carbon films. After PECVD, 9 nm and 20 nm thick silicon-doped diamond-like carbon (Si-DLC) films showed complete conversion into Q-carbon using 250eV Ar+ ions via negative biasing. However, this conversion was only partial for 30 nm thick films. Detailed EELS, XPS, Raman, and EDS studies were carried out to confirm the formation of Q-carbon by this method. We discuss the mechanism of Q-carbon formation as a result of low-energy ion bombardment during PECVD of thin films. These ions during negative biasing are energetic enough to create Frenkel defects, which support the conversion of the three-fold coordinated sp2 carbon units in as-deposited carbon into sp3 bonded five-atom tetrahedron units in Q-carbon. This process enhances the atomic number density and fraction of sp3 bonded carbon. These diamond tetrahedra are randomly packed and provide easy nucleation sites for diamond. If the underlying substrate can provide an epitaxial template for diamond growth via domain matching epitaxy, then wafer-scale growth of diamond epitaxial films can be achieved for wafer-scale integration and next-generation novel device manufacturing from diamond-related materials.

Wafer-scale solution-processed 2D material analog resistive memory array for memory-based computing

Realization of high-density and reliable resistive random access memories based on two-dimensional semiconductors is crucial toward their development in next-generation information storage and neuromorphic computing. Here, wafer-scale integration of solution-processed two-dimensional MoS2 memristor arrays are reported. The MoS2 memristors achieve excellent endurance, long memory retention, low device variations, and high analog on/off ratio with linear conductance update characteristics. The two-dimensional nanosheets appear to enable a unique way to modulate switching characteristics through the inter-flake sulfur vacancies diffusion, which can be controlled by the flake size distribution. Furthermore, the MNIST handwritten digits recognition shows that the MoS2 memristors can operate with a high accuracy of >98.02%, which demonstrates its feasibility for future analog memory applications. Finally, a monolithic three-dimensional memory cube has been demonstrated by stacking the two-dimensional MoS2 layers, paving the way for the implementation of two memristor into high-density neuromorphic computing system.

Fault-Tolerant Strong Menger (Edge) Connectivity of DCC Linear Congruential Graphs

With the rapid development and advances of very large scale integration technology and wafer-scale integration technology, multiprocessor systems, taking interconnection networks as underlying topologies, have been widely designed and used in big data era. The topology of an interconnection network is usually represented as a graph. If any two distinct vertices [Formula: see text] in a connected graph [Formula: see text] are connected by min[Formula: see text] vertex (edge)-disjoint paths, then [Formula: see text] is called strongly Menger (edge) connected. In 1996, Opatrny et al. [16] introduced the DCC (Disjoint Consecutive Cycle) linear congruential graph, which consists of [Formula: see text] nodes and is generated by a set of linear functions [Formula: see text] with special properties. In this work, we investigate the strong Menger connectivity of the DCC linear congruential graph [Formula: see text] with faulty vertices or edges, where [Formula: see text], [Formula: see text], gcd[Formula: see text] and [Formula: see text] is a multiple of [Formula: see text]. In detail, we show that [Formula: see text] is strongly Menger connected if [Formula: see text] for any [Formula: see text]. Moreover, we determine that [Formula: see text] is strongly Menger edge connected if [Formula: see text] for any [Formula: see text]. Furthermore, we prove that, under the restricted condition [Formula: see text], [Formula: see text] is strongly Menger edge connected if [Formula: see text] and [Formula: see text] for any [Formula: see text]. In addition, we present some empirical examples to show that the bounds are all optimal in the sense of the maximum number of tolerable edge faults.

Graphene-assisted metal transfer printing for wafer-scale integration of metal electrodes and two-dimensional materials

Graphene-assisted metal transfer printing for wafer-scale integration of metal electrodes and two-dimensional materials

Wafer-scale monolithic integration of full-colour micro-LED display using MoS2 transistor.

Large-scale growth of transition metal dichalcogenides and their subsequent integration with compound semiconductors is one of the major obstacles for two-dimensional materials implementation in optoelectronics applications such as active matrix displays or optical sensors. Here we present a novel transition metal dichalcogenide-on-compound-semiconductor fabrication method that is compatible with a batch microfabrication process. We show how a thin film of molybdenum disulfide (MoS2) can be directly synthesized on a gallium-nitride-based epitaxial wafer to form a thin film transistor array. Subsequently, the MoS2 thin film transistor was monolithically integrated with micro-light-emitting-diode (micro-LED) devices to produce an active matrix micro-LED display. In addition, we demonstrate a simple approach to obtain red and green colours through the printing of quantum dots on a blue micro-LED, which allows for the scalable fabrication of full-colour micro-LED displays. This strategy represents a promising route to attain heterogeneous integration, which is essential for high-performance optoelectronic systems that can incorporate the established semiconductor technology and emerging two-dimensional materials.

Photo-induced non-volatile VO2 phase transition for neuromorphic ultraviolet sensors

In the quest for emerging in-sensor computing, materials that respond to optical stimuli in conjunction with non-volatile phase transition are highly desired for realizing bioinspired neuromorphic vision components. Here, we report a non-volatile multi-level control of VO2 films by oxygen stoichiometry engineering under ultraviolet irradiation. Based on the reversible regulation of VO2 films using ultraviolet irradiation and electrolyte gating, we demonstrate a proof-of-principle neuromorphic ultraviolet sensor with integrated sensing, memory, and processing functions at room temperature, and also prove its silicon compatible potential through the wafer-scale integration of a neuromorphic sensor array. The device displays linear weight update with optical writing because its metallic phase proportion increases almost linearly with the light dosage. Moreover, the artificial neural network consisting of this neuromorphic sensor can extract ultraviolet information from the surrounding environment, and significantly improve the recognition accuracy from 24% to 93%. This work provides a path to design neuromorphic sensors and will facilitate the potential applications in artificial vision systems.