A Detailed Analysis of Wafer Scale Integration and Multichip Modules

Abstract

Hybrid integration of functional multichip layers and electronic devices has received a significant research interest from both industry and academia. While moving towards the end of Moore's law, the power consumption and device scaling remain as significant challenges, necessitating the development of beyond-multichip technologies to achieve high performance computing. While conventional techniques like wafer based bonding and pick-and-place can only partially address the aforementioned challenges, a variety of new multi-chip transfer and wafer scale circuit integration approaches have been developed. This review summarizes such wafer scale integration and neural networks based on multichip modules for many applications, such as flexible electronics, smart displays, and gaming. The proposed study has showcased a wide range of multi-chip modules, and the need for wafer scale integration with expanded functionalities. Finally, a detailed analysis on the advantages of the state-of-the-art techniques has been provided and the future research directions are discussed.