Cluster tools play a significant role in the entire process of wafer fabrication. As the width of circuits in semiconductor chips shrinks down to less than 10nm, strict operational constraints are imposed on the operations of cluster tools in order to ensure the quality of processed wafers. Particularly, wafer residency time constraints and chamber cleaning requirements are commonly seen in etching, chemical vapor deposition, coating processes, etc. They make the scheduling problem of cluster tools more challenging. This work aims to provide a solution for dual-arm cluster tools with wafer residency time constraints and chamber cleaning requirements. To do so, it proposes a novel virtual wafer-based scheduling method. By this method, under a steady state, a PM processes either a real or virtual wafer at a time. When a PM processes a virtual one, its chamber can perform a cleaning operation. In this way, we can meet not only the strict residency time constraints for real wafers, but also innovatively meet chamber cleaning requirements. Based on such a novel scheduling method, an efficient binary integer programming model is established to optimize the throughput of cluster tools. Finally, experiments are performed to show the efficiency and effectiveness of the proposed method. <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Note to Practitioners</i> —To ensure wafer quality in semiconductor manufacturing, engineers have to impose wafer residency time constraints and chamber cleaning requirements on the operations of cluster tools. In order to tackle their scheduling problem with these constraints, this work proposes a novel method based on the use of virtual wafers. Under a one-cyclic schedule obtained for time-constrained cluster tools without chamber cleaning requirements, virtual wafers are loaded into the tool such that when a PM processes a virtual wafer, a chamber cleaning operation can be performed in practice. The key to solve this scheduling problem is to find a wafer loading sequence with the highest performance in terms of cycle time. To do so, this work establishes an efficient binary integer programming model to search for such a solution. Since the obtained solution is a periodical wafer loading sequence based on a one-wafer cyclic schedule, it can be easily implemented. Therefore, this work has a high practical value to numerous semiconductor manufacturers.
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