Wafer Processing Research Articles

A reinforcement learning-based approach for solving multi-agent job shop scheduling problem

Wafer processing is the most expensive, time-consuming, and complex stage in semiconductor manufacturing. It varies significantly based on orders of customers (agents). Optimising the wafer processing flow in a multi-agent scenario can meet customised requirements, speed up delivery, and reduce costs. This work models wafer processing as a multi-agent job shop scheduling problem (MAJSP) with release dates. The objective is to minimise the total weighted makespan of agents. To address both dynamic and static scheduling scenarios in the MAJSP context, two deep reinforcement learning-based (DRL) methods are proposed. In a dynamic scheduling scenario, the statuses of orders and production resources can change at any moment. A DRL method called Graph Transformer Network (GTN) is proposed to rapidly generate high-quality solutions. In a static scheduling scenario, the production plan can be formulated based on predetermined demand and resource conditions. A novel hybrid method (GTN-DABC) that combines GTN with the discrete artificial bee colony algorithm (DABC) is proposed to provide high-quality production plans for manufacturers within an acceptable computation time. Experimental results demonstrate that the proposed GTN outperforms existing heuristics, and the well-designed GTN-DABC is more competitive than other meta-heuristics.

Atomic-scale insights into the microstructure and interface evolution mechanism of copper/tantalum nanofilms during ultra-precision grinding

The copper (Cu)/tantalum (Ta) nanofilms are the vital component in the through silicon via (TSV) wafer. However, the current lack of research on the ultra-precision machining of Cu/Ta nanofilms limits the development of TSV-based 3D integration technologies. In this work, molecular dynamics simulations are conducted to reveal the microstructure and interface evolution mechanism of Cu/Ta nanofilms during nano-grinding under various grinding depths. The results show that the material removal mode differs between the Cu and Ta layers, and the thickness of the subsurface damage layer of the Cu layer is greater than that of the Ta layer. The Cu/Ta interface is well stabilized, and small amounts of micro-defects appear only at larger grinding depths after grinding. The lattice mismatch of the constituent layers and the hindering role by the interface lead to stress concentration at the interface, and it is more obvious with increasing grinding depth. Nevertheless, there is a significant stress release after grinding. Our computations indicate that the competition between the evolution of interfacial structures and discrepancies in the physical properties of constituent layers leads to an increase in grinding forces at the interface. Furthermore, the heat transfer is obstructed by the Cu/Ta interface. This study provides valuable insights into the grinding mechanisms of Cu/Ta nanofilms, which is conducive to further improving the manufacturing process of the TSV wafer and enhancing the performance of microelectronic devices.

Ultraviolet line structuring of large solar wafers

AbstractUltrashort‐pulsed lasers are ideal for material processing by welding, marking, and cutting. Scanning systems are crucial for large substrates. We introduce a novel UV line structuring method using deformable mirror technology and freeform optics. This approach aims to improve processing times on large substrates, especially for M12 solar wafer processing. By using a freeform lens and a Zwobbel deformable mirror, we achieve extended processing fields and high scan frequencies. The paper explores optical designs, their robust optomechanical implementation for prototyping, and setup characterization.

Oxidation anisotropy of 4H-SiC wafers during chemical-mechanical polishing

4H silicon carbide (4H-SiC) wafers are widely used in high-power, high-temperature, and high-frequency electronics owing to their excellent physical and electrical properties. In the processing of 4H-SiC wafers, chemical-mechanical polishing (CMP) is commonly employed to realize atomic-scale smoothness, damage-free surface, and global planarization. The CMP process is the synergy of wet oxidation and mechanical grinding, whose efficiency significantly relies on the oxidation process. Therefore, understanding the wet oxidation mechanism of Si face and C face of 4H-SiC wafers is critical to high-efficiency double-side CMP. In this work, the anisotropic CMP performance of Si face and C face of 4H-SiC wafers are investigated. It has been found that the material removal rate of the C face is 2–3 times that of the Si face. The thicknesses of the transient oxide layer on the C face and Si face are 8.71 nm and 3.50 nm, respectively. X-ray photoelectron spectroscopy analysis reveals that the oxygen content on the C face is higher than that on the Si face after wet KMnO4 oxidation. This indicates that the C face of 4H-SiC is easier to oxidize, which results in more oxides that that on the Si face of 4H-SiC. Our work shows that accelerating the oxidation of the Si face of 4H-SiC wafers during the simultaneous double-sided CMP process is crucial for the efficient polishing of 4H-SiC wafers.

Modeling and Optimization of Wet ALE Process

Wet ALE (atomic layer etch) processes are emerging as an important alternative to standard ALE processes in semiconductor manufacturing. Here we present a model for simulating an idealized wet ALE process that includes both chemical reactions and liquid flow in order to predict the amount of material etch, how much of the etching is true ALE vs continuous etch, and its uniformity across the wafer. This model is applied to both a simple test flow cell and flow across a spinning wafer in a typical wet single wafer process. Results show that etch amount and uniformity depends on timing of the dispense steps, flow parameters, and the kinetics of the specific chemical reactions.

Fracture strength analysis of large-size and thin photovoltaic monocrystalline silicon wafers

Diamond wire slicing technology is the main method to manufacture the substrate of the monocrystalline silicon-based solar cells. With the development of technology, the size and thickness of monocrystalline silicon wafer are respectively getting larger and thinner, which cause an increase in silicon wafer fracture probability during wafer processing and post-processing. And the change of the sawing speed, saw wire diameter and abrasive size also affect the wafer’s surface characteristics, thereby affect its fracture strength. In this paper, monocrystalline silicon wafer with large size of 210 mm × 210 mm was taken as the research object, 4-point bending test was carried out on each series of silicon wafers. The load–displacement curves during bending test were collected, and the fracture stress values were calculated by finite element method. The characteristic fracture strength and Weibull modulus of each series of silicon wafers were obtained through the statistical analysis of the data using Weibull distribution function. The effect of the silicon wafer thickness, the position of the silicon wafer in the silicon brick (usage time of the saw wire varies), and the bending test direction on the fracture characteristics was analyzed. The results showed that the increase of thickness increase the characteristic fracture strength of silicon wafer. The characteristic fracture strength of the front wafers (sawn by the fresh wire) is the smallest, while the characteristic fracture strength of the middle wafers and the rear wafers (sawn by the worn wire) are similar. The characteristic fracture strength of bending in the direction of perpendicular to the saw marks is 2–3 times that of bending in the direction of parallel to the saw marks. The reason of the difference of characteristic fracture strength was analyzed based on the surface morphology, roughness, and the saw marks of silicon wafer. In this paper, the fracture characteristics of large size monocrystalline silicon wafer are studied to provide fracture data support for industry production. The mechanism and main effect factors of silicon wafer fracture are revealed, which provides directions for improving the sawing quality and reducing the fracture probability during wafer production process and post-processing.

Ultrasonic-assisted stripping of single-crystal SiC after laser modification

Laser stripping technology is an advanced processing method with high efficiency and low material loss, which can greatly reduce material loss in the production process of single-crystal SiC wafer, but the single-crystal SiC ingot still have a certain bonding force after laser modification. Ultrasonic vibration can reduce the bonding force and thus strip single-crystal SiC wafer. In order to investigate the effect of ultrasonic vibration on the reduction of the bonding force of single-crystal SiC internal modification layer, through the ultrasonic-assisted stripping of single-crystal SiC orthogonal experiment, the ultrasonic vibration parameters of ultrasonic frequency, vibration time and ultrasonic power of the three indexes of the reduction of the bonding force was analyzed. The results show that the bonding force of the modified layer decreased by 25 %–60 % after ultrasonic vibration. Variance analysis of the experiment results showed that the main factors influencing the bond strength reduction were vibration time and ultrasonic power in turn. When the vibration time is longer and the ultrasonic power is higher, the stripping force decreases more, and the stripping force of single-crystal SiC wafers decreases up to 60 % under the condition of vibration time of 5min and ultrasonic power of 700 W. Through analysis of the single-crystal SiC cross-section, distinct cleavage steps and cleavage channels are evident. The laser-modified region exhibits defect such as nano-pores, micro-cracks, and nano-particles.After the single-crystal SiC laser modification process was upgraded, the distance between the ultrasonic tool head and the single-crystal SiC was 1.5 mm can directly strip off the single-crystal SiC wafer. And eventually stripped 6-inch single-crystal sic wafers. Therefore, ultrasonic vibration can increase the internal defects in the single-crystal SiC modified layer, causing crack expansion to occur and ultimately stripping the single-crystal SiC wafer.

Dicing Process for 4H-SiC Wafers by Plasma Etching Using High-Pressure SF<sub>6</sub> Plasma with Metal Masks

Since SiC is hard and brittle, dicing by normal grinding process not only requires a long time for processing, but also reduces chip strength due to microcracks. The use of highly efficient and damage-free etching with high-pressure plasma as a chemical processing method for dicing rather than mechanical processing was investigated. The results of groove processing using a combination of a metal mask with slit-like apertures and plasma etching with high-pressure SF6 plasma showed that the processing speed decreased with decreasing slit width and increasing groove depth. The results of electrostatic field calculations suggest that this is due to a decrease in plasma intensity caused by electric field decreasing.

HYPREZ Wafering Solutions: A Novel Approach of SiC Wafering Solution

A novel approach for processing SiC wafers has been developed to grind then polish 150 and 200mm SiC wafers without lapping. The purpose of this work was to optimize the processing of SiC wafers sliced from boules to finished epi-ready wafers by grinding and chemical-mechanical polishing (CMP). Diamond vitrified wheels were used for coarse and fine grinding to correct the irregular shape of SiC wafers before reducing surface roughness by CMP. 4H-SiC wafers were sliced by diamond embedded/slurry wire saw and laser split techniques. Incoming wafer condition was seen to affect coarse grinding wheel performance depending on incoming surface roughness and shape. Wheel characteristics, including abrasive size, abrasive concentration, and bond structure, were adjusted to improve grinding efficiency based on incoming conditions. Coarse grinding wheels were able to reduce wafer total thickness variation to 3-5um and average surface roughness to 20-30nm (Ra). Fine grinding wheels were optimized to reduce total thickness variation (TTV) below 2um and surface roughness to 1-2nm Ra and peak-to-valley height of 20-30nm (Rt). Coarse and fine wafering time was less than 30 minutes total to remove 50 microns on both Si and C-face per wafer. Surface damage from grinding was removed after one hour of polishing each wafer by CMP, achieving surface roughness of 0.4nm Ra and 5-7nm Rt. The benefit of optimizing coarse and fine grinding of 150 and 200mm SiC wafers is demonstrated by producing flat wafers, which reduced overall processing time to prepare an epi-ready condition by CMP.

A Novel Contactless SiC Wafer Planarization Processing after Mechanical Slicing by Dynamic Thermal Annealing Processes

In conventional machining of SiC wafers, material loss and sub-surface damage (SSD) of both the front and back surfaces are major issues. In this study, we focused on Dynamic AGE-ing® (DA), which is a sublimation-controlled process, and applied it to the total wafering process without any mechanical contact of both the front and back surfaces to explore the possibilities to reach the CMP-equivalent quality. DA process enables material lossless planarization of SiC wafers by applying a temperature gradient to achieve simultaneous etching and growth at the same rate on one and the other surfaces, respectively. To drive the planarization function for a multi-wire saw finished as-sliced wafer, as an example, a high-temperature regime above 2000 °C under an Ar background pressure higher than 1 kPa to suppress etching and growth rates was employed as the first step in the DA treatment. In this step, an effective annealing function arises where sublimation and recrystallization occur simultaneously through a sub-surface region on both sides of the wafer. Due to the active interchange of the surface and subsurface layer, a self-organizing planarization effect occurs on a macroscopic scale on both surfaces with the removal of SSD. The conventional DA processes were employed for the following microscopic flatness control. As a result, the roughness of the 6-inch as-sliced wafer was reduced to 0.7 nm on the Si-face and 2.0 nm on the C-face while maintaining the wafer thickness. This is the first promising result exhibiting the potential of thermal contactless treatment for next-generation wafer manufacturing by improving quality and cost.

Study on the polishing performance and mechanism of sapphire wafers by different types of degradable surfactants

Traditional chemical-mechanical polishing (CMP) slurry suffers from significant environmental pollution, and easy reaggregation of ultra-fine abrasives, all of which hinder its further application. In this study, the processing performance and mechanism of three different degradable surfactants to sapphire wafers were investigated, utilizing degradable aminomethylpropanol and xylitol as pH regulator and complexing agent of polishing slurry, respectively, which is aimed at solving the problem of the easy agglomeration of ultra-fine abrasives while achieving the super-precision and pollution-free process of sapphire wafers. After polishing, the surface roughness (Sa) of sapphire wafers decreases from 7.240 nm to 0.396 nm, which is 44.8 % lower than that without surfactant. Only <1 nm is the PV value, and there is a 12.9 % increase in the material removal rate. The action mechanism of biodegradable surfactants during CMP was revealed through TEM, XPS, electrochemical testing, contact angle measurement, and particle size analysis. The results showed that surfactants can effectively improve the wettability of the polishing slurry on the wafer and the dispersity of the ultra-fine abrasives in the slurry, thus facilitating the interfacial reaction between the sapphire surface and polishing slurry and the homogeneity of the material removal. This work truly realizes a green and pollution-free process that meets the requirements of ultra-smooth and efficient polishing of sapphire wafers.

Novel and Low-Cost Techniques for Extending the Etch Capabilities of an Inductively Coupled Plasma Etch Tool That Has Clamp Fingers for Clamping 4-Inch Diameter Wafers

Widening the processing capabilities of an inductively coupled plasma (ICP) etch tool by “preventing wafer breakage” during processing of wafers, or by gaining the capability to do “through-wafer silicon etch” are important challenges that may need to be resolved with very limited resources. Resolving the undesired wafer breakage issues caused during processing of wafers is important to reduce the manufacturing costs, and increase production yield. Furthermore, considering the high prices of the state-of-the-art wafer processing tools, it is also important to prevent wafer breakage by using low-cost approaches especially if the resources for purchasing state-of-the-art processing equipment are not available. Two novel methods (method #1, and method #2) are developed to prevent wafer breakage and allow through-wafer silicon etching. With method #1, an aluminium alloy ring (AAR) and an o-ring are employed to obtain uniform load distribution (instead of point loads) on the required outer region on the surface of a wafer, and to minimize or completely remove the bending moment that may be formed on the possible cross-sections of the entire wafer, during clamping of the wafer. With method #2, through-wafer silicon etching is made possible by simultaneous application of method #1 and addition of a helium cooling gas (HCG) leakage blocking dicing tape at the back side of the wafer that is under processing for through-wafer etching. By using the explained methods, wafer breakage during ICP etch processing is eliminated, and through-wafer silicon etching is made possible. From the other side, the effective wafer area that can be used for processing is reduced by 48%. Novel and capability enabling 2 different techniques that are extremely low-cost compared to purchasing a state-of-the-art ICP etch tool are presented to extend the processing capabilities of an ICP etch tool for deep silicon etching (method #1), and through-wafer silicon etching (method #2).

Investigation of Cu Corrosion Defects Induced by Humidity Imbalance in the Cu Damascene Process of Semiconductors

As integrated circuit design rules shrink in semiconductor, Copper (Cu) has been employed as the back end of line (BEOL) interconnect metal to enhance device performance through reduced resistivity and resistive-capacitive delay.[1] However, Cu metal lines are prone to degradation caused by Cu oxidation-induced defects, including extrusions and voids, owing to their inherent properties.[2] Consequently, it becomes essential to regulate the oxidation rate during the chip fabrication process, particularly when the Cu metal line is exposed during the Damascene process. This control is crucial for ensuring long-term reliability and achieving a higher yield.[3]From the learning of earlier technological nodes, we are aware to and already precisely controlling both process queue time and wafer surface humidity. We must exercise control over the queue time, addressing both inter-process intervals and in-process queuing. [4] This underscores the importance of managing queue time and maintaining low environmental humidity to mitigate wafer surface defects when the FOUP (Front Opening Unified Pod) is opened at the EFEM (Equipment Front End Module).[5] Those humidity and queue times related Cu corrosion defects have been mitigated by N2 purge in FOUP and reducing the wafer quantity. However, dividing the lot, typically consisting of 25 wafers, by half or less to reduce queue times leads to an imbalance in low humidity due to N2 purging. This occurs when the FOUP is opened in EFEM.This paper examines Cu corrosion under low humidity conditions in a FOUP with a small quantity of wafers, specifically examining the influence of queue time during N2 purging in the EFEM. Through simulation of the interaction between the inlet air entering the EFEM and the purged N2 gas, a vulnerable area is identified where copper oxidation takes place. In addition, we propose an arrangement to mitigate high humidity, supported by experiments conducted under real equipment conditions.Fig. 1 shows Cu corrosion defects after ILD etching at around 20% RH in the FOUP. This defect is only observed in the lower slot of the FOUP on the N2 purged load port. Figure 2 illustrates a chart depicting the humidity inside the FOUP under various conditions. The humid region within the FOUP when opened on the N2 purged load port without wafers. (Fig.2a) While the extent of the humid area is contingent upon the flow rate of the N2 purge and the intake of air through the Fan Filter Unit (FFU), the vortex of the inlet air from the cleanroom (<42% RH) is notably observed at the bottom and front side of the FOUP. Therefore, wafers stored in the lower slot of the FOUP face an increased risk of Cu corrosions when subjected to elevated humidity levels during processes like ILD etching and subsequent cleaning. Specifically, an extended queue time amplifies the probability of Cu defects occurring in this high-humidity slot compared to slots with lower humidity. We observed an unintended increase to 28.2% RH in specific configurations when reducing the quantity of wafers to minimize queue time. (Fig. 2b)Hence, we propose an arrangement for wafers that maintains low humidity with small quantity. When placing 12 wafers in the FOUP, an arrangement with equal spacing from the first slot to the 25th slot ensures uniform N2 flow, thereby reducing the highest humidity from 28.2% RH to 14.0% RH by half. (Fig.3a) Alternatively, positioning all wafers on the upper section is another method. (Fig.3b) Therefore, by halving the quantity of wafers and reducing the process wait time by half, and applying the optimal wafer arrangement that maintains low humidity balance even with a small number of wafers, we confirmed the absence of Cu corrosion.

(Invited) Novel Brush Design for Post CMP Cleans

Chemical Mechanical Polishing (CMP) process is one of the key processes in semiconductor wafer processing. A sub 10nm wafer fabrication process may require more than 40 dielectric and metal CMP steps. As CMP process requirements get more stringent, CMP slurries are formulated with smaller and smaller metal oxide abrasive particles. The abrasive particles may also be surface modified or doped with other metal oxides. Post CMP cleaning chemistry formulations are designed to remove polish byproducts, pad residues and abrasive particles from wafer surface. Chemical composition and PH are tuned for modulating wafer surface-particle interactions so brushes can mechanically “sweep” them off the surface. PVA brushes, used of post CMP cleans, are a highly porous network of crosslinked polyvinyl acetate with pore size in the range of 30 – 100 um and 80% - 90% porosity, depending on the type of brush being used. While PVA brushes have largely met the process capability requirements, they have limitations for advanced cleans such as nano-particle removal. As CMP process continues to expand to new dielectric and metal films for different process steps in wafer fabrication, there is a need for customized brush material and surface design for optimal cleaning efficiency.We discuss a new engineered post CMP brush design that shows high efficiency in nano-particle cleans and allows high level of material tunability. New brush design is an engineered composite with an open cell microporous core, overlaid with engineered fibers in form of loops. Brush design is compatible with existing post CMP cleans. Figure 1(a) shows the new design, where in DIW enters the brush through the center of microporous core and flows outwards to the surface. As water exits the surface, it flows over and across the loops and contacts the wafer surface. Flow resistance through core and loops can be independently tuned, which allows better fluid distribution and more effective cleans. Figure 1(b) show a close-up schematic of interaction between loop and particle. Flexing of the loops on brush surface provides improved contact as well as cleaning ability Brush design can be optimized for chemical and mechanical properties with choice of fiber material, fiber diameter and loop height. Figure 2 shows the Zeta potential of PVA and different loop materials. The fiber material maybe selected such that zeta potential of the loops can enhance mechanical action in removing particle. Mechanical action of the Loops can be modeled as a cantilever and force on the particle is exerted by flexing of the loops.Deflection of loops can be approximated with flexure stiffness of rods with point load at free end. For initial purposed loop is approximated as single element. The equation can be rewritten to calculate cleaning force P at the free end for given loop deflection (Y), P = 3EIY/L3 (1)Where E is elastic modulus, I = moment, L = length of fiber and for rod shapes; I = Pi*(r4/4)The adhesion of particles on the surface is due to the effect of van der Waals and electrostatic forces. The total adhesion force on the surface can be written as: F=F vdw + F edl (2) where Ft is total adhesion force, Fvdw is the van der Waals force, and Fedl is the electrostatic force.Fvdw = AR/6r2 (3)Where A is the Hamaker constant, R is particle radius, r is the separation distanceFor effective removal of particles, P >/= F (4)Flex force and adhesion force were modeled based on equation (1) and (3) and are shown in Figure 3. New brush design was used for post CMP cleaning of silicon dioxide wafers polished with ceria slurry. Two different brush designs were tested for cleaning efficiency. Modeling data and comparison with experimental results is presented. Figure 1

Kinematic mechanics study of silicon wafers and glass particles oscillatory separation based on friction coefficient differences

In this paper, the static friction coefficient of different particle sizes silicon wafers, glass particles and separation platform are measured by the plane method. Based on the force analysis of particle oscillatory separation process, the kinetic equation of particle oscillatory separation process is established, and the influence of factors such as particle size and friction coefficient on the motion trajectory of particle oscillatory separation process is analyzed. The research results indicate that the range of static friction coefficients between silicon wafers, glass particles, and separation platforms is different, but there are also overlapping parts. The kinetic equation indicates that the motion speed of particle oscillatory separation process is affected by factors such as the friction coefficient between particles and separation platforms, the inclination angle of separation platforms, and the amplitude of separation platforms. During the oscillatory separation process of silicon wafer glass mixed particles, silicon wafer particles with friction coefficients of 0.33–0.39 will become silicon wafer products, glass particles with friction coefficients of 0.22–0.31 will become glass products, and silicon wafer glass particles with overlapping friction coefficients of 0.310.33 will become intermediate products. To achieve better separation of silicon wafer and glass particles in the oscillatory separation process, it is necessary to take control measures to reduce the friction coefficient between the separation platform and silicon wafer and glass particles as much as possible.

Analysis of Subsurface Damage Structures of Gallium Nitride Substrates Induced by Mechanical Polishing with Diamond Abrasives

Subsurface damage (SSD) structures induced by mechanical polishing of gallium nitride (GaN) substrates are comprehensively investigated using atomic force microscopy, cathodoluminescence (CL) imaging, and cross‐sectional transmittance electron microscopy. The low removal rate of the CMP process is a barrier to high productivity of a GaN wafering process; therefore, reducing the chemical mechanical polishing (CMP) process time by reducing the depth of SSD induced by mechanical processing is an active research area. To better understand the SSD structures, the surface roughness, SSD depth, and SSD distributions induced by mechanical polishing are quantitatively evaluated in this study. The SSD structures induced by mechanical polishing can be quantitatively exhibited as the SSD distribution with the damage strength at the outermost surface and the damage propagation, which are obtained by CMP process time‐resolved CL imaging method. On the basis of the analysis results, a schematic model of the SSD structures for mechanically polished GaN substrates is proposed.

Polishing performance and material removal mechanism in the solid-phase Fenton reaction based polishing process of SiC wafer using diamond gel disc

The use of SiC wafer is widespread in many fields, especially in aerospace, energy, 5 G communications, and microelectronics. Chemical-mechanical polishing (CMP) is the primary method used for achieving an ultra-smooth surface on SiC wafers. However, CMP suffers from low efficiency, leading to increased processing time and costs. To address this issue, we developed a novel diamond gel polishing disc that incorporates SiO2/Fe3O4 (S/F) powder. The disc enhances polishing efficiency through a solid-phase Fenton reaction between the disc and SiC. The research investigates the reaction mechanism and the material removal model of the polishing process using SEM, TEM, and XPS analysis. Experimental studies are conducted to assess the polishing performance and validate the effectiveness of the theoretical model. The findings indicate that SiC undergo a solid-phase Fenton reaction with polishing disc mixed S/F powder (SG-S/F disc) during polishing. The Fenton reaction generates hydroxyl radicals (·OH), which break the Si-C and Si-Si bonds in the crystal structure, leading to the formation of a softer nanoscale amorphous oxide layer on the SiC surface. The cyclic generation and removal of this oxide layer enable highly efficient polishing of SiC wafers. Compared to a gel disc without S/F (SG disc), SiC polished with the SG-S/F disc exhibits superior surface quality. Additionally, the material removal rate (MRR) of the SG-S/F disc reaches 1.42 μm/h, representing a 51.1 % improvement over that of the SG disc. These results clearly demonstrate that the solid-phase Fenton reaction significantly enhances the polishing performance of the gel polishing disc.

Cycle time analysis for cluster tools with parallel process chambers, processing time variation, and chamber cleaning operations

Cluster tools are the key equipment in semiconductor manufacturing. For high-end chip manufacturing processes, to ensure the wafer quality, periodical cleaning operations for process chambers in such tools are required for eliminating the residual gas and chemicals. In operating a tool, the wafer processing time in a process chamber may vary within a range. It is meaningful to predict the cycle time of cluster tools with chamber cleaning operations and processing time variation. By doing so, automation material handling system can be told when a lot is completed by a cluster tool such that it can assign an overhead hoist transporter to transport this lot at the right time. This plays an important role in improving the productivity of a whole semiconductor manufacturing system. This work conducts the cycle time analysis of cluster tools with chamber cleaning operations and processing time variation. Specifically, it proposes a novel method to calculate the average cycle time of a single-arm cluster tool under which an optimal schedule can be obtained. Then, for a dual-arm cluster tool, an efficient algorithm is developed to approximate the average system cycle time under which an optimal schedule can be obtained. Experiments show that the gap between the average system cycle time obtained by simulations and the average system cycle time obtained by the proposed method is no more than 0.1% which demonstrate the effectiveness of the proposed method.

Low-oxygen silicon preparation using vacuum treatment by oxidation control and moisture removal kinetics investigation

Diamond wire saw silicon powder (DWSSP) is a waste produced during silicon wafer processing for photovoltaic (PV) modules, and it shows significant reutilization potential. However, the presence of moisture leads to silicon oxidation and the formation of a surface SiO2 layer that hinders the recovery of high-purity silicon. In this study, vacuum treatment (VT) was used to prepare low-oxygen silicon by controlling the oxidation and removing moisture from DWSSP waste, thus preventing SiO2 layer formation. The oxygen content in DWSSP decreased by 15.01 %, from 7.26 % to 6.17 %, and the SiO2 layer thickness also decreased by 10.29 %, from 2.04 nm to 1.83 nm after the VT process. Additionally, the VT process lowered the moisture boiling point, facilitating surface evaporation and internal diffusion of moisture. This increased the moisture effective diffusion coefficient from 5.16 × 10−10–6.16 × 10−9 m2 s−1 to 1.21 × 10−9–6.88 × 10−9 m2 s−1 and reduced the apparent activation energy from 32.17 kJ mol−1 to 16.05 kJ mol−1. The efficient moisture removal of VT inhibited the growth of the SiO2 layer to enable the preparation of low-oxygen silicon during silicon recovery.

2D Fractal Arrays of Ultrathin Silicon Nanowires as Cost‐Effective and High‐Performance Substrate for Supercapacitors

Silicon is the most diffused material in the industry; thus, considering its high capacity for energy storage, silicon‐based materials are well studied as battery anodes and supercapacitors. Si nanowires (NWs) emerge due to the high surface to volume ratio, its compatibility with a wafer processing typical of microelectronics, and are studied as anodes for lithium batteries as well as coupled with other materials for supercapacitor application. In this article, the synthesis and application are reported as a lithium anode of 2D fractal arrays of ultrathin Si NWs obtained by a thin‐film metal‐assisted chemical etching (MACE). These Si NWs exhibit a density of about 1012 NWs cm−2, maximizing the surface to volume ratio compared to silver‐salts MACE and other NW fabrication approaches. By using 2.7 μm long NWs, a pseudo‐capacitor behavior with a specific capacitance of about 274.2 μF cm−2 at a scan rate of 50 mV s−1 is obtained. This specific capacitance is two orders of magnitude higher than the one obtained in the same condition by using NWs synthesized by silver‐salt MACE. In this result, the route is opened toward the application of these fractal arrays of ultrathin Si NWs as substrate for supercapacitors with improved efficiency.