Wafer-level Packaging Structure Research Articles

Reliability Assessment of Wafer Level Package using Artificial Neural Network Regression Model

ABSTRACTFor electronic packaging structure, there are many design parameters that will affect its reliability performance, using experimental way to obtain the reliability result will take a considerable amount of time. Therefore, how to shorten the design time becomes a critical issue for new electronic packaging structure development. This research will combine artificial intelligence (AI) and simulation technology to assess the long-term reliability of wafer level packaging (WLP). A simulation technology using finite element method (FEM) with appropriate mechanics theories has been validated by multiple experiments will replace the experiment to create reliability results for different WLP structures. After a big WLP structure-reliability database created, this study will apply artificial neural network (ANN) theory to analyze this database and obtains a regression model for structure-reliability relationship of WLP. Once the regression model is established and validated, the WLP geometry, such as pad size, die and buffer layer thickness, and solder volume, etc. can be simply entered, and then the WLP reliability results can be immediately obtained through the ANN regression model.

High-brightness LEDs of big chip size on multi-layer interconnects with optimized thermal dissipation and optical performance

The market share of high-brightness LEDs in general lighting has been rapidly expanding mainly owing to the continued technological advances on internal quantum efficiency, light extraction and wavelength conversion. In spite of these promising advances, there remain some key breakthroughs to be made before LED lighting technology can be fully adopted into the broad market, with emphasis on efficient thermal dissipation, higher efficacy at high brightness, and low manufacturing cost. Higher brightness requires LEDs to be operated at higher current density which results in efficacy degradation due to droop behavior and thus higher power loss into heat and shorter lifetime. Therefore a highly efficient mechanism of thermal dissipation is needed for timely conduction of heat away from the high-power LED chip. For general lighting at high brightness, a large chip size is preferable. More importantly, with larger chip size, higher brightness can be achieved at much lower current density which leads to less degradation of efficacy. However simply increasing the die size of LEDs in wafer fabrication causes significant yield loss and thus hinders the adoption of big-chip LEDs. In this paper we propose a scalable approach to enable larger chip sizes for manufacturing high efficacy & high brightness LEDs at high yield and low cost. The metric of lower cost per lumen is necessary for LEDs to be competitive to traditional light sources like fluorescent lights in the consumer market segment. About 50% of the total LED production cost is consumed by the packaging processes after the emissive device stack being fabricated. Also given the minimal thickness of the device stack, the key bottleneck for thermal dissipation resides in the packaging structure and its interface to the device stack. We address these two key challenges with a novel wafer-level packaging structure of metal contacts forming a perimeter that is integrated into the device stack, which optimizes the thermal dissipation rate from the active device stack to substrate while allowing high aperture ratio and improved light output. Our approach applies a wafer-level batch process starting from LED fabrication to packaging for internal and external light extraction as well as wavelength conversion, in order to achieve high throughput and high yield in a scalable and inexpensive manner. To improve the overall power efficiency, different materials have been selected for ohmic contacts and high reflectivity at p and n electrodes, and further developments continue to be implemented, including a current-spreading layer, large-area light extraction structure and integrated phosphor material. Flip chip packaging is chosen due to its advantage of full front-side emission, maximized aperture ratio, compact form factor, higher integration density and ease of wafer level processing. The substrates for flip chip packaging of LED chips are made of Si which was selected due to its relatively high thermal conductivity (149 W/m/K) and ease of fabrication with standard semiconductor processes. Multi-layer interconnects are patterned over the Si substrate with solder bumps built over the passivation openings for flip-chip assembly of multiple LED dies. The multi-layer dielectric stack of the substrate is designed to form dielectric mirror maximizing the reflection of emitted light back into the LED side for improved light output.

Design and Fabrication of a Low-cost Wafer-level Packaging for RF Devices

This paper presents the structure and process technology of simple and low-cost wafer-level packaging (WLP) for thin film radio frequency (RF) devices. Low-cost practical micromachining processes were proposed as an alternative to high-cost processes, such as silicon deep reactive ion etching (DRIE) or electro-plating, in order to reduce the fabrication cost. Gold (Au)/Tin (Sn) alloy was utilized as the solder material for bonding and hermetic sealing. The small size fabricated WLP of <TEX>$1.04{\times}1.04{\times}0.4mm^3$</TEX> had an average shear strength of 10.425 <TEX>$kg/mm^2$</TEX>, and the leakage rate of all chips was lower than <TEX>$1.2{\times}10^{-5}$</TEX> atm.cc/sec. These results met Military Standards 883F (MIL-STD-883F). As the newly proposed WLP structure is simple, and its process technology is inexpensive, the fabricated WLP is a good candidate for thin film type RF devices.

Wafer level packaging for high-brightness LED lighting with optimized thermal dissipation and optical performance

High-brightness LED lighting has gained high attention in the industry and its market share for general lighting has been rapidly expanding upon the continued progress on improving internal quantum efficiency, light extraction and wavelength conversion. In spite of these promising advances, some key breakthroughs must be made before this technology can be fully adopted into the broad market, such as efficient thermal dissipation and low manufacturing cost. A lion share of cost of an LED module is incurred during the packaging processes after the emissive device stack has been fabricated. Also given the thin thickness of device stack, the packaging structure remains the bottleneck for thermal dissipation. We address these two key challenges with a novel wafer-level packaging structure integrated into the device stack, which enables maximal thermal dissipation rate from active device stack to substrate while allowing high aperture ratio and optimized light output. Our approach applies full wafer-level batch process from epitaxial growth all the way down to packaging for internal and external light extraction as well as wavelength conversion, in order to achieve high throughput and high yield in a scalable and inexpensive manner. Initial prototypes of GaN based blue LED with big chip size have been fabricated without selective electrodes for minimal contact resistance, exhibiting high brightness at relatively low drive voltage (3.5V). As one key step in wafer level packaging, the wafer bonding process was characterized with Moire patterning and Topography and Deformation Measurement to understand the warpage profile and varying temperatures along both heat up and cool down paths, with simulation performed in guidance to final solution for compensating the warpage profile along the bonding process and afterwards. Different approaches were applied in learning the most effective bonding technique for this packaging structure. Further development is ongoing to improve the overall power efficiency and color quality, including optimal materials for ohmic contacts at both electrodes, current-spreading layer, large-area light extraction structure, and integrated phosphor material. This wafer-level packaging technology is scalable to large wafer size for high-throughput and low-cost manufacturing, to achieve both superior thermal management and optimized power efficiency.

Design and optimization of thermo-mechanical reliability in wafer level packaging

In this paper, a variety of wafer level packaging (WLP) structures, including both fan-in and fan-out WLPs, are investigated for solder joint thermo-mechanical reliability performance, from a structural design point of view. The effects of redistribution layer (RDL), bump structural design/material selection, polymer-cored ball application, and PCB design/material selection are studied. The investigation focuses on four different WLP technologies: standard WLP (ball on I/O WLP), ball on polymer WLP without under bump metallurgy (UBM) layer, ball on polymer WLP with UBM layer, and encapsulated copper post WLP. Ball on I/O WLP, in which solder balls are directly attached to the metal pads on silicon wafer, is used as a benchmark for the analysis. 3-D finite element modeling is performed to investigate the effects of WLP structures, UBM layer, polymer film material properties (in ball on polymer WLP), and encapsulated epoxy material properties (in copper post WLP). Both ball on polymer and copper post WLPs have shown great reliability improvement in thermal cycling. For ball on polymer WLP structures, polymer film between silicon and solder balls creates a ‘cushion’ effect to reduce the stresses in solder joints. Such cushion effect can be achieved either by an extremely compliant film or a ‘hard’ film with a large coefficient of thermal expansion. Encapsulated copper post WLP shows the best thermo-mechanical performance among the four WLP structures. Furthermore, for a fan-out WLP, it has been found that the critical solder balls are the outermost solder balls under die-area, where the maximum thermal mismatch takes place. In a fan-out WLP package, chip size, other than package size, determines the limit of solder joint reliability. This paper also discusses the polymer-cored solder ball applications to enhance thermo-mechanical reliability of solder joints. Finally, both experimental and finite element analysis have demonstrated that making corner balls non-electrically connected can greatly improve the WLP thermo-mechanical reliability.

Designing for reliability using a new Wafer Level Package structure

Wafer Level Packages are one of the most advanced packaging concepts. It combines the advantages of flip chip with conventional surface mount technologies. In recent years, we have seen a tremendous growth in the application of Wafer Level Packages, both in quantities as well as in the number of products where they are implemented. The technology is, however, not without it is challenges with 1st and 2nd level reliability issues. For instance, the limit on the size of Wafer Level Packages has to do with the 2nd level, or solder bump, reliability. This paper highlights our major research and development results on understanding and enhancing the 1st and 2nd level reliability of Wafer Level Packages using combined experimental and virtual prototyping (thermal, mechanical and thermo-mechanical) techniques. Typical 1st level reliability problems within Wafer Level Packages are cracking of repassivation materials, fatigue of bond over active pads, and cracks within the Under Bump Metalisation. Typical 2nd level problems concern solder fatigue and brittle fractures within the intermetallics. To investigate the physics of failure for these problems, dedicated parametric finite element models are constructed including the thin IC layers. Two structures are explored to their potential reliability benefits, being the traditionally used repassivation structure and a newly developed Bump on Active structure. This so-called BUMA structure makes use of a thick Al buffer layer. By combining the experimental results with reliability prediction models, both structures in terms of 1st and 2nd level reliability performance are explored. Based on the results we have designed and manufactured an improved construction that significantly outperforms current solutions.

A wafer-scale packaging structure with monolithic microwave integrated circuits and passives embedded in a silicon substrate for multichip modules for radio frequency applications

A wafer-level packaging structure with chips and passive components embedded in a silicon substrate for multichip modules (MCM) is proposed for radio frequency (RF) applications. The packaging structure consists of two layers of benzocyclobutene (BCB) films and three layers of metalized films, in which the monolithic microwave ICs (MMICs), thin film resistors, striplines and microstrip lines are integrated. The low resistivity silicon wafer with etched cavities is used as a substrate. The BCB films serve as interlayer dielectrics (ILDs). Wirebonding gold bumps are used as electric interconnections between different layers, which eliminate the need of preparing vias by costly procedures including dry etching, metal sputtering and electroplating. The chemical mechanical planarization (CMP) is used to uncover the gold bumps, and the BCB curing profile is optimized to obtain the appropriate BCB film for CMP process. In this work, the thermal, mechanical, electrical as well as RF properties of the packaging structure are investigated. The packaging thermal resistance can be controlled below 2 °C W−1. The average shear strength of the gold bumps on the BCB surface is about 70 MPa. In addition, a Kelvin test structure is fabricated for resistance testing of the vertical vias. The performances of MMIC and interconnection structure at high frequency are simulated and tested. The testing results reveal that the slight shifting of S-parameter curves of the packaged MMIC indicates perfect transmission characteristics at high frequency. For the transition structure of transmission line, the experimental results are compatible with the simulation results. The insertion loss (S21) is below 0.4 dB from 0 to 40 GHz and the return loss (S11) is less than −20 dB from 0 to 40 GHz. For a low noise amplifier (LNA) chip, the S21 shifting caused by the packaging structure is below 0.5 dB, and S11 is less than −10 dB from 8 GHz to 14 GHz.