Wafer-level Packaging Process Research Articles

A miniaturized and low-loss Q-band SIW bandpass filter based on evanescent-mode in wafer-level packaging process

This paper presents a miniaturized Q-band substrate integrated waveguide (SIW) bandpass filter (BPF) on a silicon-based wafer-level packaging (WLP) process. By incorporating capacitive quasi-coplanar waveguide (CPW) feeding structures and complementary split-ring resonators (CSRRs), the SIW operates in an evanescent-mode below the lower cutoff frequency and then achieves miniaturization. The efficient conversion of wave-modes, mutual excitation among multiple capacitive structures, and extremely short transmission paths, collectively resulting in the proposed BPF exhibiting low insertion loss. Furthermore, the area of fabricated filter has been reduced by 88.96 % compared to the requirement of the cutoff frequency. The measured results show that the minimum insertion loss is 1.24 dB, the return loss is better than 15 dB, and the 3 dB passband covers from 29.6 to 47.8 GHz (FBW is 47 %). These results indicate that, the proposed filter effectively solve the issues of large areas in SIW filters and high losses in silicon-based integrated or packaging processes.

링 공진기의 체배종속적 전류분포 해석을 통한 Molding Compound의 광대역 유전율 측정 방법 연구

In this study, we propose an algorithm that complements the frequency dependence of the relative permittivity conversion equation applied for the measurement of relative permittivity through a ring resonator. The broadband electrical characteristics of an epoxy molding compound (EMC) used in the fan-out wafer-level packaging (FOWLP) process were measured using our algorithm. By proposing a formula for calculating the permittivity that reflects the current distribution at the multiplied frequency of the microstrip ring resonator, the effective range of the permittivity of the sample was extended to the multiplied frequency region. Thus, a more sophisticated and effective complex permittivity was calculated over a wide band. The relative permittivity of the EMC measured by the proposed technique was 3.836 and the dielectric loss tangent was 0.022. This technique improved the relative permittivity measurement error rate by 3.95 % and the measurement error rate of the dielectric loss tangent by 8.4 %p compared to the conventional method.

Investigation of Warpage for Multi-Die Fan-Out Wafer-Level Packaging Process.

This paper focuses on characterizing the evolution of warpage, effects of epoxy molding compound (EMC), and effects of carrier 2 (the second carrier in the process) of 12 inch RDL-first multi-die fan-out wafer-level packaging (FOWLP) during the manufacturing process. The linear viscoelasticity properties of EMC and polyimide (PI) were characterized using dynamic mechanical analysis (DMA) in the frequency domain at different temperatures., The elastic and viscoelastic model were used for PI and EMC, the finite element analyses (FEA) of the cured structure were carried out and the results were compared with the test results. The viscoelastic properties of the EMC in the FEA could predict the wafer warpage more accurately. The FEA and experiments were used to investigate the evolution of warpage. The molding had a great influence on the warpage. The effects of the EMC and carrier 2 were also investigated with FEA. The wafer warpage could be reduced by lowering the thickness of the EMC, increasing the thickness of carrier 2, and selecting EMC and carrier 2 with a matched coefficient of thermal expansion (CTE).

Design and Implementation of RF Front-End Module Based on 3D Heterogenous-Integrated Wafer-Level Packaging

In this paper, a three-dimensional heterogenous-integrated (3DHI) wafer-level packaging (WLP) process is proposed, and a radio frequency (RF) front-end module with two independent ultra-high frequency (UHF) receiving channels are designed and implemented, which covers 400 MHz–600 MHz and 2050 MHz–2200 MHz respectively for unmanned aerial vehicle (UAV) applications. The module is formed by wafer-to-wafer (W2W) bonding of two high-resistivity silicon (HR-Si) interposers with embedded bare dies and through silicon via (TSV) interconnections. Double-sided deep reactive ion etching (DRIE) and conformal electroplating process are introduced to realize the high-aspect-ratio TSV connection within 290 µm-thick cap interposer. Co-plane waveguide (CPW) transmission lines are fabricated as the process control monitor (PCM), the measured insertion loss of which is less than 0.18 dB/mm at 35 GHz. The designed RF front-end module is fabricated and measured. The measured return loss and gain of each RF channel is better than 13 dB and 21 dB, and the noise figure is less than 1.5 dB. In order to evaluate the capability of the 3DHI process for multi-layer interposers, the module is re-designed and fabricated with four stacked high-resistivity silicon interposers. After W2W bonding of two pairs of interposers and wafer slicing, chip-to chip (C2C) bonding is applied to form a four-layer module with operable temperature gradient.

Warpage Simulation During Fan-Out Wafer-Level Packaging Process with Uncertainty of Material Properties.

Along with the reduction in semiconductor chip size and enhanced performance of electronic devices, high input/output density is a desired factor in the electronics industry. To satisfy the high input/output density, fan-out wafer-level packaging has attracted significant attention. While fan-out wafer-level packaging has several advantages, such as lower thickness and better thermal resistance, warpage is one of the major challenges of the fan-out wafer-level packaging process to be minimized. There have been many studies investigating the effects of material properties and package design on warpage using finite element analysis. Current warpage simulations using finite element analysis have been routinely conducted with deterministic input parameters, although the parameter values are uncertain from the manufacturing point of view. This assumption may lead to a gap between the simulation and the field results. This paper presents an uncertainty analysis of wafer warpage in fan-out wafer-level packaging by using finite element analysis. Coefficient of thermal expansion of silicon is considered as a parameter with uncertainty. The warpage and the von Mises stress are calculated and compared with and without uncertainty.

Experimental and theoretical investigation of bifurcated wafer warpage evolution in the wafer level packaging processes

Wafer warpage, which mainly originated from thermal mismatch between the materials, has become serious in wafer level packaging (WLP) as larger diameter and thinner wafers are required currently. In this paper, three-dimensional wafer warpage profile and the warpage evolution during typical fan-in WLP processes including wafer thinning process were characterized in situ. Special attention was paid to the bifurcated phenomenon. Prior to the wafer thinning process, the wafer deformed into a bowl shape which was caused by polyimide (PI) curing. A distinct bifurcation behavior appeared and the wafer warped into a cylindrical shape when the wafer was thinned below 270 μm. This bifurcation behavior was systematically analyzed by theoretical analysis and finite element analysis (FEA). Equivalent material model method and perturbation method were employed to simplify the FEA model and incur the bifurcation behavior, respectively.

Effect of Thermal Cycling on the Thermal and Mechanical Properties of Dielectric Materials

Photosensitive polymers or dielectric materials such as polyimides (PIs) have been used in fan-out wafer-level packaging process (FOWLP) as a redistribution layer for quite some time. In the condensed 2-D and 3-D packaging processes, the dielectric materials are applied multiple times to create as many as four or five redistribution layers. At the end of the process, the first layer may experience up to four times of heat cycles in which the polymer properties may change. However, the effect of heat cycles on properties of dielectric film as well as their contributions to the wafer-level warpage is still unclear. To understand the changes of materials’ properties after several heat cycles, the thermal and thermo-mechanical properties of negative-tone and positive-tone types of dielectric films are characterized by using the thermomechanical analysis (TMA), dynamic mechanical analysis (DMA), and thermogravimetric analysis (TGA). The glass transition temperature ( ${T}_{g}$ ), coefficient of linear thermal expansion (CTE), and modulus (storage, ${E}'$ , and loss, ${E}''$ ) are analyzed and compared. In addition, the morphology of the films before and after heat cycles is also analyzed.

A modelling and simulation approach for radio frequency (RF) parasitic effects reduction in wafer-level packaging (WLP) of RF-MEMS passive components

RF-MEMS, i.e. micro electro mechanical-systems (MEMS) for radio frequency (RF) passive components, started to make their way into mass-market applications in the telecommunication segment. One critical aspect to ensure easy employment of such devices within systems and sub-systems is that of packaging and encapsulation. In packaging of RF-MEMS, next to the protection of the fragile movable structures and membranes, optimisation of the package electrical performance plays a very important role. In this work, a wafer-level packaging process is investigated and optimised in order to minimise its electrical parasitic effects. The capping silicon substrate resistivity, the substrate thickness and the geometry of through-silicon vias are optimised relying on finite element method electromagnetic simulations. Moreover, a preliminary analysis on the electromagnetic effects of the wafer-to-wafer bonding techniques (i.e. solder bump reflow and Isotropic or anisotropic conductive adhesive – ICA/ACA) is presented.

Low-temperature Cu-Cu thermocompression bonding for encapsulation of a MEMS mirror

Abstract In this study, a low temperature wafer-level packaging process aimed for encapsulating MEMS mirrors was developed. The glass cap wafer used in the package has an antireflective (AR) coating that limits the maximum temperature of the bonding process to 250°C. Copper thermocompression was used as copper has a high self-diffusivity and the native oxidation on copper surfaces can be completely removed with combination of ex situ acetic acid wet-etch and in situ forming gas anneal. Making it suitable for a development of a low temperature bonding process. In this work, bonding on of sputtered and electrodeposited copper films was studied on temperatures ranging from 200°C to 300°C as well as the effect of pretreatment on bond strength. The study presents a successful thermocompression bonding process for sputtered Cu films at a low temperature of 200°C with high yield of 97 % after dicing. The bond strength was recorded to be 75 MPa, well above the MIL-STD-883E standard (METHOD 2019.5) rejection limit of 6.08 MPa. The high dicing yield and bond strength suggest that the thermocompression bonding could be possible even at temperatures below 200°C. However, the minimum bonding temperature was not yet determined in this study.

Advances in Temporary Bonding and Debonding Technologies for use with Wafer-Level System-in-Package (WLSiP) and Fan-Out Wafer-Level Packaging (FOWLP) Processes

AbstractToday's complex fan-out wafer-level packaging (FOWLP) processes include the use of redistribution layers (RDL) and reconstituted wafers with epoxy mold compound (EMC) for use in heterogeneous integration [1]. Wafer-level system-in-package (WLSiP) uses fan-out wafer-level packaging (FOWLP) to build the system-in-package (SiP) by attaching know-good die (KGD) in a chip-first process to a tape laminated temporary carrier. If the dies are attached in a die-up configuration (active area facing up) and then over-molded with EMC, contact pads on the embedded die are exposed during the backside grind process. During the RDL build, the temporary carrier supplies mechanical support for the thinned substrate. In a die-down configuration with the active area facing down (eWLB), the temporary carrier is removed after the molding process thus exposing the contact pads for RDL build and solder ball mount.The ideal chip attachment scheme should minimize lateral movement of the die during over-mold (die shift) and also minimize vertical deformation of the bonding material. Thermal release tape provides a convenient way to attach die to a carrier prior to over-molding with EMC. However, not all bonding materials are suitable for presentation in tape form, so the material used in the tape may not be the optimal choice. An alternative method is to directly apply temporary bonding material to the carrier substrate. This enables the use of bonding materials with higher melt viscosity and improved thermal stability, resulting in less vertical deformation during die placement, and reduced die shift during over-molding. The bonding material will ideally have high adhesion to the EMC wafer to prevent delamination in the bond line during downstream processing. Stack stress and warpage is a major concern which causes handling and alignment problems during processing. The bonding material and carrier will need to be specifically suited to minimize the effects of stress in the compound wafer.Such material must balance rigidity with warp to prevent lateral die shift and deformation induced by coefficient of thermal expansion (CTE) mismatch between the carrier and EMC material [2]. Bonding materials must also have enough adhesion to the EMC material to overcome such stress without bond failure for an associated debond path (such as laser or mechanical release). In this experiment, we will examine a thermoplastic bonding material in combination with different release materials, addressing die shift, and deformation after EMC processing. Successful pairs will then undergo carrier release using either mechanical release or laser ablation release technology.

A study of Sub-micron Fan-out Wafer Level Packaging solutions

Abstract In Fan-out Wafer Level Packaging (FOWLP) processes, redistribution layer (RDL) line width reduction is a key challenge to expand the FOWLP market to multi-chip interconnections, including interconnections between SoC and DRAM, split-die connection of FPGA, and interconnections between image sensors and SoC. Next generation FOWLP requires 1.0 μm RDL and future FOWLP is targeting 0.8 μm RDL. To meet these requirements, Canon has developed new projection optics with a high NA and wide-field that is best suited for sub-micron FOWLP. These projection optics are a new option for FPA-5520iV steppers, offering NA 0.24 imaging and a 52 × 34 mm exposure field. FPA-5520iV steppers with NA 0.24 provide excellent 0.8 μm resolution performance throughout all imaging fields thanks to Canon's wave-front aberration based projection optics manufacturing methods and on-axis optical tilt focus sensor.

Fine Pitch(40μm) Integration Platform for Flexible Hybrid Electronics using Fan-Out Wafer-level Packaging

Abstract A flexible fan-out wafer-level packaging (FOWLP) process for heterogeneous integration of high performance dies in a flexible and biocompatible elastomeric package (FlexTrateTM) was used to assemble 625 dies with co-planarity and tilt <1μm, average die-shift of 3.28 μm with σ < 2.23 μm. Fine pitch interconnects (40μm pitch) were defined using a novel corrugated topography to mitigate the buckling phenomenon of metal films deposited on elastomeric substrates. Corrugated interconnects were then used to interconnect 200 dies, and then tested for cyclic mechanical bending reliability and have shown less than 7% change in resistance after bending down to 1 mm radius for 1,000 cycles.

Eutectic-based wafer-level-packaging technique for piezoresistive MEMS accelerometers and bond characterization using molecular dynamics simulations

We developed a eutectic-based wafer-level-packaging (WLP) technique for piezoresistive micro-electromechanical systems (MEMS) accelerometers on the basis of molecular dynamics analyses and shear tests of WLP accelerometers. The bonding conditions were experimentally and analytically determined to realize a high shear strength without solder material atoms diffusing to adhesion layers. Molecular dynamics (MD) simulations and energy dispersive x-ray (EDX) spectrometry done after the shear tests clarified the eutectic reaction of the solder materials used in this research. Energy relaxation calculations in MD showed that the diffusion of solder material atoms into the adhesive layer was promoted at a higher temperature. Tensile creep MD simulations also suggested that the local potential energy in a solder material model determined the fracture points of the model. These numerical results were supported by the shear tests and EDX analyses for WLP accelerometers. Consequently, a bonding load of 9.8 kN and temperature of 300 °C were found to be rational conditions because the shear strength was sufficient to endure the polishing process after the WLP process and there was little diffusion of solder material atoms to the adhesion layer. Also, eutectic-bonding-based WLP was effective for controlling the attenuation of the accelerometers by determining the thickness of electroplated solder materials that played the role of a cavity between the accelerometers and lids. If the gap distance between the two was less than 6.2 µm, the signal gains for x- and z-axis acceleration were less than 20 dB even at the resonance frequency due to air-damping.

Reduction of Thermal Stress - Part III: UBM and Passivation Thickness Optimization

Abstract Integration of Back End Of Line (BEOL) CMOS technologies with Wafer Level Packaging (WLP) is challenging, as mismatch of Coefficient of Thermal Expansion (CTE) between materials can result in thermo-mechanical induced cracking. This is especially true during reflow cooling of wafers after the solder ball attach process. Factors that contribute towards cracking can be from both the BEOL as well the WLP process steps. Finite Element Analysis (FEA) of such designs can help identify possible root causes early in the design process and i.e. before actual fabrication. This would help save valuable prototyping & testing costs. In Part III of this series of FEA studies, two factors i.e. silicon nitride thickness (from the BEOL process), and the Under Bump Metalization (UBM) thickness (from the WLP process) were identified as significant factors in changing the maximum first principal stress levels in the passivation layer.

A mega-trend-diffusion grey forecasting model for short-term manufacturing demand

Accurate short-term demand forecasting is critical for developing effective production plans; however, a short forecasting period indicates that the product demands are unstable, rendering tracking of product development trends difficult. Determining the actual developing data patterns by using forecasting models generated using historical observations is difficult, and the forecasting performance of such models is unfavourable, whereas using the latest limited data for forecasting can improve management efficiency and maintain the competitive advantages of an enterprise. To solve forecasting problems related to a small data set, this study applied an adaptive grey model for forecasting short-term manufacturing demand. Experiments involving the monthly demand data for thin film transistor liquid crystal display panels and wafer-level chip-scale packaging process data showed that the proposed grey model produced favourable forecasting results, indicating its appropriateness as a short-term forecasting tool for small data sets.

Novel glass substrates for minimizing thermal stress development during electronic device packaging process

Abstract Glass can be utilized for support or career substrate in large size packaging process since it has excellent mechanical and optical properties. However, the thermal stress caused by a mismatch of coefficient of thermal expansion (CTE) causes an unneglectable warpage during a thermal process. In order to overcome this thermal stress issue, we have developed novel glasses that have finely tuned CTE characteristics to fit each packaging process. In this paper, we will report on a glass substrate whose CTE is perfectly matched with that of Si, and a series of glass substrates whose CTEs are controlled in sub-ppm order and within the range of 3.3 ~ 12.0 ppm/°C. To evaluate the effect of glass CTE on the thermal stress management, the warpage behavior of Si wafer after glass wafer bonding were investigated by both numerical simulation and experiment. Both results indicate that a small CTE mismatch can cause an unneglectable wafer warpage during the thermal process. Thus sub-ppm order control of glass CTE is essential for minimizing thermal stress development in large size packaging process. The glass substrate with Si matched CTE is suitable for the process where glass and Si are contact directly, e.g. Si back grinding process or through glass via (TGV) technology. The series of glass substrates whose CTEs are finely controlled in a high range are useful when the packaging process utilizes high amount of resins, such as Fan-Out wafer level packaging process.

Compensation Method for Die Shift Caused by Flow Drag Force in Wafer-Level Molding Process.

Wafer-level packaging (WLP) is a next-generation semiconductor packaging technology that is important for realizing high-performance and ultra-thin semiconductor devices. However, the molding process, which is a part of the WLP process, has various problems such as a high defect rate and low predictability. Among the various defect factors, the die shift primarily determines the quality of the final product; therefore, predicting the die shift is necessary to achieve high-yield production in WLP. In this study, the die shift caused by the flow drag force of the epoxy molding compound (EMC) is evaluated from the die shift of a debonded molding wafer. Experimental and analytical methods were employed to evaluate the die shift occurring during each stage of the molding process and that resulting from the geometrical changes after the debonding process. The die shift caused by the EMC flow drag force is evaluated from the data on die movements due to thermal contraction/expansion and warpage. The relationship between the die shift and variation in the die gap is determined through regression analysis in order to predict the die shift due to the flow drag force. The results can be used for die realignment by predicting and compensating for the die shift.

BCB-Based Dry Film low k Permanent Polymer with sub 4-μm Vias for Advanced WLP and FO-WLP Applications

There is a strong demand to increase the routing density of the RDL to match the requirements for future microelectronic systems which are mainly miniaturization and performance. Photo-resists for structuring the metallization or acting as a mold for electroplating are common for very fine lines and spaces due to the developments in the front-end processing. For example chemical amplified Photo-resists are now moving in the back-end and wafer level packaging process. The results are mainly governed by the performance of the equipment i.e. the photo-tool. This is different for the permanent dielectric polymer material. The major difference in photo-resists and dielectric photo-polymer are the different functions of the material systems. Photo-resists are only temporary masks for subsequent process steps like etching and plating. This is different for the photo-polymers which are a permanent part of the future systems. In this paper a new technology is discussed which uses a laser scanning ablation process and BCB-Based Dry Film low k Permanent Polymer. Laser ablation of polymers is in principle not a new technology. Low speed and high cost was the major barrier. But the combination of a scanning technology together with quartz masks has opened this technology to overcome the limitation of the current photo-polymer process. The new technology is described in detail and the results of structuring BCB-Based Films down to less than 4 μm via diameter in a 15 μm thick film has been shown. The via side wall can be controlled by the fluence of the laser pulse. Test structures have been designed and fabricated to demonstrate the excellent electrical resistivity of the vias using a two-layer metallization process.

A Theoretical Study on Post-It-Like Debonding Process for BCB Cap Transfer Packaging Based on FEM Simulation

This paper presents ANSYS finite-element method analysis of wafer-level Benzocyclobutene cap transfer packaging process utilizing simple and easy detachment of the carrier wafer. The detachment has been implemented through hydrophobic monolayer coating of Si carrier wafer surface before BCB cap patterning. Razor blade insertion between the Si carrier and device wafer is used to separate the BCB cap from the carrier wafer. The debonding is regarded as interfacial fracture between Si and BCB, and thus the monolayered interface is modeled with ANSYS cohesive zone model. BCB cap's deformation and resultant stress during the debonding are principal interests of the modeling as it determines whether the transfer succeeds or fails. For this purpose, typical load-displacement curves of crack analysis are studied to comprehend the debonding behavior of the BCB cap in the course of Si carrier detachment. It is found that the BCB cap size is a critical parameter for the debonding process as interfacial toughness is proportional to the BCB cap dimension. And thicker BCB cap is more efficient to the debonding in terms of necessary opening displacement and developed maximum stress. In addition, cap material property such as Young's modulus has significant effect on the debonding behavior.

A novel mechanical diced trench structure for warpage reduction in wafer level packaging process

The wafer warpage problem, mainly originated from coefficient of thermal expansion mismatch between the materials, becomes serious in wafer level packaging as large diameter wafer is adopted currently. The warpage poses threats to wafer handling, process qualities, and can also lead to serious reliability problems. In this paper, a novel mechanical diced trench structure was proposed to reduce the final wafer warpage. Deep patterned trenches with a depth about 100μm were fabricated in the Si substrate by mechanical dicing method. Both experiment and simulation approaches were used to investigate the effect of the trenches on the wafer warpage and the influence of the geometry of the trenches was also studied. The results indicate that, by forming deep trenches, the stress on the individual die is decoupled and the total wafer warpage could be reduced. The final wafer warpage is closely related to the trench depth and die width. Trenched sample with a depth of 100μm can decrease the wafer warpage by 51.4%.