Novel glass substrates for minimizing thermal stress development during electronic device packaging process

Abstract

Listen

Translate article

Abstract Glass can be utilized for support or career substrate in large size packaging process since it has excellent mechanical and optical properties. However, the thermal stress caused by a mismatch of coefficient of thermal expansion (CTE) causes an unneglectable warpage during a thermal process. In order to overcome this thermal stress issue, we have developed novel glasses that have finely tuned CTE characteristics to fit each packaging process. In this paper, we will report on a glass substrate whose CTE is perfectly matched with that of Si, and a series of glass substrates whose CTEs are controlled in sub-ppm order and within the range of 3.3 ~ 12.0 ppm/°C. To evaluate the effect of glass CTE on the thermal stress management, the warpage behavior of Si wafer after glass wafer bonding were investigated by both numerical simulation and experiment. Both results indicate that a small CTE mismatch can cause an unneglectable wafer warpage during the thermal process. Thus sub-ppm order control of glass CTE is essential for minimizing thermal stress development in large size packaging process. The glass substrate with Si matched CTE is suitable for the process where glass and Si are contact directly, e.g. Si back grinding process or through glass via (TGV) technology. The series of glass substrates whose CTEs are finely controlled in a high range are useful when the packaging process utilizes high amount of resins, such as Fan-Out wafer level packaging process.