Wafer Level Packaging Technology Research Articles

Wafer Level Packaging to Address Future Direct Chip Attach Needs

This paper covers results from early pathfinding investigations of a wafer level package (WLP) technology that addresses future direct chip attach (DCA) needs. An overview of the WLP technology and pathfinding results covering key process flow evaluations and future challenges to apply the concept to DCA are presented. Proof-of-concept (POC) of 300mm wafer-level mold integrating with Cu bumps was demonstrated by investigating the mold thickness uniformity, wafer warpage, and solder joint reliability on the board. We conclude with a discussion of the key risk areas remaining challenges that includes the mold grinding thickness variance control, optimization of the material properties, and alternative low cost bumping technologies scalable less than 0.3mm pitch, and outline the next steps to continue data collection on the wafer warpage behavior, the die breakage strength, and the board level assembly process using a standard surface mount infrastructure in our pathfinding work.

MEMS Wafer-level Packaging Technology Using LTCC Wafer

SUMMARY This paper describes a versatile and reliable wafer-level hermetic packaging technology using an anodically bondable low-temperature co-fired ceramic (LTCC) wafer, in which multilayer electrical feedthroughs can be embedded. The LTCC wafer allows many kinds of microelectromechanical systems (MEMS) to be more flexibly designed and more easily packaged. The hermeticity of vacuum-sealed cavities was confirmed after 3000 cycles of thermal shock (–40 30 min/+125 30 min) by the diaphragm method. To practically apply the LTCC wafer to a variety of MEMS, the electrical connection between the MEMS on a Si wafer and feedthroughs in the LTCC should be established by a simple and reliable method. We have developed a new electrical connection method: the electrical connection is established by porous Au bumps, which are part of the Au vias exposed in wet-etched cavities on the LTCC wafer. A 100% yield of both electrical connection and hermetic sealing was demonstrated. A thermal shock test up to 3000 cycles confirmed the reliability of this packaging technology.

ChipletT, A Cost-Effective, High Reliability, Embedded Die Fan-Out Package Based on Multilayer Flex Laminate with Enhanced Thermal Performance

Fan-Out Wafer Level Packaging (FO-WLP) technology has been developed in recent years to overcome the limitations of Fan-in WLP (FI-WLP) packages and to add more functionality to WLP. Fan-Out packages expand the WLP market to higher pin count devices and add multiple die System in Package (SiP) capability. In this paper, a novel approach to low cost fan-out packaging based on polyimide flex circuits and wafer level Embedded Die Customization (EDC) is discussed. ChipletT refers to Fan-Out packaging. ChipsetT refers to System in Package developed with WABE (Wafer and Board Level Embedding) technology. WABE technology is based on co-lamination of multi layer polyimide flex wiring and conductive z-axis sintered metal interconnections. Using WABE technology, ultra thin fan-out packages (0.4mm) can be fabricated with lower processing costs, higher throughput and with 3D extendibility. Embedded Die Customization is performed at the wafer level and involves optimization of the die-to-embedding process by using optimized wafer level processing capabilities including polymer processing, copper plating and wafer thinning. Reliability of the ChipletT packages, both component level and board level is evaluated. ChipletT packages show high reliability in component level testing and board level testing (Thermal Cycling and Drop Testing). The thermal performance of ChipletT packages were also evaluated in this study. Thermal resistance parameters θja and θjc were simulated with and without thermal vias for both face up and face down configurations. ChipletT provides a new low cost fan out packaging option with proven component level and board level reliability performance.

A 3‐dB Quadrature WLP Coupler for 60 GHz Applications

ABSTRACTA 60 GHz tandem coupler using offset broadside coupled lines is proposed in a WLP (Wafer Level Packaging) technology. The fabricated coupler has a core chip area of 750 μm × 385 μm (0.288 mm2). The measured results show an insertion loss of 0.44 dB, an amplitude imbalance of 0.03 dB and a phase difference of 87.6° at 60 GHz. Also the measurement shows an insertion loss of less than 0.67 dB, an amplitude imbalance of less than 0.31 dB, a phase error of less than 3.7°, an isolation of more than 29.7 dB and a return loss of more than 27.9 dB at the input ant coupled ports and more than 14.3 dB at the direct and isolated ports over the frequency band of 57-66 GHz, covering 60 GHz band both in Japan and US. To the best of our knowledge the proposed coupler achieves the lowest ever reported insertion loss and amplitude imbalance for a 3-dB coupler on a silicon substrate. With its superior performance and lower cost compared to the CMOS counterparts, the proposed coupler is a suitable candidate for low-cost high-performance millimeter-wave systems.

Wafer level packaging compatible with millimeter-wave antenna

This paper presents a technological process compatible process compatible with an above integrated circuit (IC) to achieve a millimeter wave antenna structure that is well-suited for wafer level packaging technology. The radiating patch is introduced inside of the air cavity of packaging. This structure consists of two dielectric substrates and benzocyclobutene (BCB) sealing rings at the wafer level. The wafer level packaging that holds the radiating patch is made of Pyrex, a low permittivity substrate. The millimeter-wave antenna using the micromachining technology is excited by a coplanar waveguide fed aperture (CPWFA). This feeding mechanism is designed and realized on GaAs, a high permittivity substrate. The electromagnetic energy of the CPWFA to the radiating patch is made through a coupling slot. The fabricated antenna of 6 mm × 6 mm, including the ground plane, exhibits a 10 dB bandwidth of 3 GHz from 50.5 GHz to 53.5 GHz. The design has been driven by the interest of collective encapsulation of MEMS and MMICs devices.

Flexible Chip-on-Flex (COF) and embedded Chip-in-Flex (CIF) packages by applying wafer level package (WLP) technology using anisotropic conductive films (ACFs)

Due to increasing demand for higher performance, greater flexibility, smaller size, and lighter weight in electronic devices, extensive studies on flexible electronic packages have been carried out. However, there has been little research on flexible packages by wafer level package (WLP) technology using anisotropic conductive films (ACFs) and flex substrates, an innovative packaging technology that requires fewer process steps and lower process temperature, and also provides flexible packages. This study demonstrated and evaluated the reliability of flexible packages that consisted of a flexible Chip-on-Flex (COF) assembly and embedded Chip-in-Flex (CIF) packages by applying a WLP process. The WLP process was successfully performed for the cases of void-free ACF lamination on a 50 μm thin wafer, wafer dicing without ACF delamination, and a flip-chip assembly which showed stable bump contact resistances. The fabricated COF assembly was more flexible than the conventional COF whose chip thickness is about 700 μm. To evaluate the flexibility of the COF assembly, a static bending test was performed under different bending radiuses: 35 mm, 30 mm, 25 mm, and 20 mm. Adopting optimized bonding processes of COF assembly and Flex-on-Flex (FOF) assembly, CIF packages were then successfully fabricated. The reliability of the CIF packages was evaluated via a high temperature/humidity test (85 °C/85% RH) and high temperature storage test (HTST). From the reliability test results, the CIF packages showed excellent 85 °C/85% RH reliability. Furthermore, guideline of ACF material property was suggested by Finite Element Analysis (FEA) for better HTST reliability.

Wafer-level packaging and direct interconnection technology based on hybrid bonding and through silicon vias

The presented wafer-level packaging technology enables the direct integration of electrical interconnects during low-temperature wafer bonding of a cap substrate featuring through silicon vias (TSVs) onto a MEMS device wafer. The hybrid bonding process is based on hydrophilic direct bonding of plasma-activated Si/SiO2 surfaces and the simultaneous interconnection of the device metallization layers with Cu TSVs by transient liquid phase (TLP) bonding of ultra-thin AuSn connects. The direct bond enables precise geometry definition between device and cap substrate, whereas the TLP bonding does not require a planarization of the interconnect metallization before bonding. The complete process flow is successfully validated and the fabricated devices’ characterization evidenced ohmic interconnects without interfacial voids in the TLP bond.

SiP(System in Package) Solutions with Wafer Level Packaging Technology

In mobile application, the WLP technology has been developing to make whole package size almost same as chip size. However, the I/O per chip unit area has increased so that it gets difficult to realize ideal pad pitch for better reliability. Recently, to achieve the thin and small size, high performance and low cost semiconductor package, Embedding Die and Fanout Technologies have been suggested and developed based on wafer level processing. In this work, as a solution of system in package, wafer level embedded package and fanout technology will be reviewed. Firstly, Wafer level embedded System in Package (WL-eSiP) which has daughter chip (small chip) embedded inside mother chip (bigger chip) without any special substrate has been suggested and developed. To realize wafer level embedded system in package (WL-eSiP), wafer level based new processes like wafer level molding for underfilling and encapsulation by molding compound without any special substrate have been applied and developed, including high aspect ratio Cu bumping, mold thinning and chip-to-wafer flipchip bonding. Secondly, Fan-out Package is considered as alternative package structure which means merged package structure of WLCSP (wafer level chip size package) and PCB process. We can make IC packaging widen area for SIP(System in Package) or 3D package. In addition, TSV and IPD are key enabling technology to meet market demands because TSV interconnection can provide wider bandwidth and high transmission speed due to vertical one compared to wire bonding technology and IPD can provide higher performance, more area saving to be assembled and small form factor compared to discrete passive components.

Flip Chip and Wafer Level Packaging - Past, Present and Future

Flip chip packaging was developed nearly 50 years ago by IBM for the purposes of improved reliability and automated semiconductor assembly. For the first 35 years the use of flip chip technology was limited to a few large IDMs and automotive companies. Beginning fifteen years ago, companies providing flip chip bumping services were established. The primary reason for adoption of flip chip in the 1990s was to enable higher I/O count chips and to improve the power and ground distribution through the use of area array interconnects. Beginning in the early 2000s high speed serial links and other I/O with fast edge rates required the use of flip chip interconnects to improve signal propagation. In the future a greater percentage of devices will utilize flip chip interconnects as these chip requirements continue to drive increased demand. Future challenges include the requirements for better power and ground distribution, finer pitch interconnects and higher I/O count devices while protecting the every more fragile inter layer dielectrics (ILDs) present on the device. Wafer Level Package (WLP) technology was developed approximately fifteen years ago to address form factor requirements in mobile products. Today WLPs play an ever increasing role in both mobile and other applications. An understanding of the market drivers, technology limitations, and variety of WLP structures used will be reviewed from both a historical perspective and current implementation. The breadth of products that are currently packaged with WLPs will also be reviewed. The principal challenges for WLPs both today and historically has been to provide adequate thermal cycle reliability and drop test capability for ever increasing device sizes and ball counts. Future market requirements for WLP technology will likely require new structures that can be cost effectively produced.

300mm Scaling of Critical Silicon Etches for Image Sensor Wafer-Level Packaging Based on Tessera's MVP (TSV) Technology

Miniature, high performance camera modules are found in a range of consumer devices including phones, PDAs, cameras and gaming consoles. According to Gartner the $1B image sensor market will grow to $2.3B by 2013. Image sensor packaging technologies are increasingly required to deliver greater reliability within smaller form factors. Tessera's OptiML™ Micro Via Pad (MVP) wafer-level packaging technology is in production on 200mm wafers. This paper will report on the first joint activity that scales this technology to 300mm. We focus on three critical silicon etches that form the back-bone of the structure. These etches are carried out from the wafer back-side while bonded to a glass carrier. First there is a blanket dry etch. This removes stress introduced by the back-grind. Uniformity control to < ±5% is essential for this process. Second, after a lithography step, tapered silicon trenches are etched forming streets to a certain depth. The trench etch uniformity is critical because it defines the depth range for the subsequent Vias. Profile control is needed to ease the subsequent spray-coat lithography. Lastly, vias are then etched down to metal bond pads on the device side of the wafer. CD and taper control is required here both within wafer and between wafers. End-pointing represents a way of ensuring process reproducibility. In 2010 Tessera carried out 300mm demos with key suppliers. As part of this activity SPTS scaled the above critical silicon etches. The wafers were further processed into functional die. We will describe the etch equipment used, report on the critical processes developed emphasizing the relationships between 200mm and 300mm results and the essential control parameters. We will also demonstrate successful scaling by including data on the electrical performance of packaged devices.

Ultrathin WLP Die Embedded Polyimide Multi-Layer Wiring Board

We have developed an ultrathin IC-embedded polyimide multi-layer wiring board utilizing a wafer level packaging (WLP) technology. The IC die is wafer level packaged with no solder bump (i.e. just copper land), thinned less than 100 micron and then sandwiched between multi-layer printed wiring boards composed of thin polyimide films with the thickness of several tens of microns used in standard flex boards. Therefore, the realized embedded board has a very thin structure, e.g. the thickness of a 4 layers board with 1 die embedded is 220 micron. For the electrical connection between circuit layers including redistribution layer of the embedded die, the means employed in our standard wiring board process is applied. The electrical connection is made by the conductive paste, which consists of several kinds of metal filler and resin adhesive and makes alloy between copper of circuit layer thorough pressing and heating processes. The alloying feature of the paste assures the robustness of the connection. The reliability of the board under several environmental test conditions has been confirmed so far, however, the board performance under bending stress was unclear. The realized board is still flexible and bendable to some extent, although the board has higher stiffness than standard flex board owing to its multi-layer structure. To confirm whether this feature affect on the board's performance or not, we have investigated the performance of the embedded board under the condition that the bending stress is applied to the die embedded die. The experimental results show no significant change due to the bending stress and the high durability against bending is confirmed.

Three Axes MEMS Combined Sensor for Electronic Stability Control System

A microelectromechanical systems (MEMS) combined sensor measuring two-axis accelerations and an angular rate (rotation) has been developed for an electronic stability control system of automobiles. With the recent trend to mount the combined sensors in the engine compartment, the operation temperature range increased drastically, with the request of immunity to environmental disturbances such as vibration. In this paper, we report the combined sensor which has a gyroscopic part and two acceleration parts in single die. A deformation-robust MEMS structure has been adopted to achieve stable operation under wide temperature range (-40 to 125°C) in the engine compartment. A package as small as 10 × 19 × 4 mm is achieved by adopting TSV (through silicon via) and WLP (wafer-level package) technologies with enough performance as automotive grade.

Ultra-Wideband Power Divider Using Multi-Wafer Packaging Technology

A compact ultra-wideband Wilkinson power combiner/divider is first demonstrated using a hermetic multi-wafer wafer level packaging technology. Its bandwidth is broadened to around 2-22 GHz with a maximum VSWR around 2:1, by using a multi-section design approach. A total of four sections are adopted to achieve better than 20 dB isolation between output ports across the majority of a 3-19 GHz band. The first two stages are implemented on the first wafer, with the last two stages on the second wafer. This configuration significantly reduces the chip size and volume and makes the multi-section wideband divider viable for monolithic microwave integrated circuit implementation. To the authors' knowledge, this is the smallest Wilkinson power divider ever reported for such a wide bandwidth.

Wafer Level Packaging of Compound Semiconductors

The microelectronics industry has implemented a number of different wafer level packaging (WLP) technologies for high volume manufacturing, including: UBM deposition, solder bumping, wafer thinning, and dicing. These technologies were successfully developed and implemented at a number of contract manufacturing companies, and then licensed to many of the semiconductor manufacturers and foundries. The largest production volumes for these technologies are for silicon-based semiconductors. Continuous improvements and modifications to these WLP processes have made them compatible with the changes observed over the years in silicon semiconductor technologies. These industry changes include: the move from aluminum to copper interconnect metallurgy, increases in wafer size, decreases in pad pitch, and the use of Low-K dielectrics. In contrast, the direct transfer of these WLP technologies to compound semiconductor devices, like GaAs, SiC, InP, GaN, and sapphire; has been limited due to a number of technical compatibility issues, several perceived compatibility issues, and some business concerns From a technical standpoint, many compound semiconductor devices contain fragile air bridges, gold bond pads, topographical cavities and trenches, and have a number of unique bulk material properties which are sensitive to the mechanical and chemical processes associated with the standard WLP operations used for silicon wafers. In addition, most of the newer contract manufacturing companies and foundries have implemented mostly 200 and 300 mm wafer capabilities into their facilities. This limits the number of places that one can outsource the processing of 100 and 150 mm compound semiconductor wafers. Companies that are processing large numbers of silicon based semiconductor wafers at their facilities are reluctant to process many of these compound semiconductors because there is a perceived risk of cross contamination between the different wafer materials. Companies are not willing to risk their current business of processing silicon wafers by introducing these new materials into existing process flows. From a business perspective, many companies are reluctant to take the liability risks associated with some of the very high-value compound semiconductors. In addition, the volumes for many of the compound semiconductor devices are very small compared with silicon based devices, thus making it hard to justify interruption in the silicon wafer flows to accommodate these lower volume products. In spite of these issues and perceptions, the markets for compound semiconductors are expanding. Several high profile examples include the increasing number of frequency and power management devices going into cell phones, light emitting diodes, and solar cells The strategy for the work described in this paper is to protect all structures and surfaces with either a spin-on resist or a laminated film during each step in the process flow. These layers will protect the wafer from mechanical and chemical damage, and at the same time protect the fab from contamination by the compound semiconductor.

Lateral Back-to-Back Diode for Low-Capacitance Transient Voltage Suppressor

In this paper, a transient voltage suppressor (TVS) using a native lateral back-to-back diode structure in conventional complementary metal–oxide–semiconductor (CMOS) technology is proposed. The capacitance, direct-current (DC) current–voltage (I–V) characteristics, and transmission line pulse (TLP) I–V characteristics of this lateral back-to-back diode are investigated. An optimization guideline for the lateral device is presented. The lateral structure is also suitable for the advanced wafer-level chip-scale package (WL-CSP) technology to meet the low capacitance and small footprint requirement for high-frequency or handheld device applications. This is a simple solution for a low-capacitance and low breakdown-voltage protection device against electrostatic discharge and electrical overstress in discrete or on-chip applications.

Beamforming Lens Antenna on a High Resistivity Silicon Wafer for 60 GHz WPAN

Wafer-scale beamforming lenses for future IEEE802.15.3c 60 GHz WPAN applications are presented. An on-wafer fabrication is of particular interest because a beamforming lens can be fabricated with sub-circuits in a single process. It means that the beamforming lens system would be compact, reliable, and cost-effective. The Rotman lens and the Rotman lens with antenna arrays were fabricated on a high-resistivity silicon (HRS) wafer in a semiconductor process, which is a preliminary research to check the feasibility of a Rotman lens for a chip scale packaging. In the case of the Rotman lens only, the efficiency is in the range from 50% to 70% depending on which beam port is excited. Assuming that the lens is coupled with ideal isotropic antennas, the synthesized beam patterns from the S-parameters shows that the beam directions are -29.3°, -15.1°, 0.2°, 15.2°, and 29.5 °, and the beam widths are 15.37°, 15.62°, 15.46°, 15.51°, and 15.63°, respectively. In the case of the Rotman lens with antenna array, the patterns were measured by using on-wafer measurement setup. It shows that the beam directions are -26.6°, -21.8°, 0°, 21.8°, and 26.6° . These results are in good agreement with the calculated results from ray-optic. Thus, it is verified that the lens antenna implemented on a wafer can be feasible for the system-in-package (SiP) and wafer-level package technologies.

Reliability Verification of Hermetic Package With Nanoliter Cavity for RF-Micro Device

With the advance of high-performance and small-size microelectromechanical systems (MEMS) devices, wafer-level packaging has gained increased attention over the past few years. Most MEMS packages must protect the often-fragile mechanical structures against the environment and provide the interface for the interaction with the next level in the packaging hierarchy. It is obvious that stable performance and high reliability are essential requirements of a packaged device. In this paper, a novel hermetic package, called the WL-¿P, recently developed for radio-frequency (RF)-filter and RF-duplexer, will be reviewed in terms of its construction, fabrication process, and electrical/mechanical performance. The package consists of a device wafer for a MEMS device and a cap wafer that has a micromachined cavity and through-wafer vias for electrical connections. The cap and device wafers are bonded to each other through a closed square loop of gold/tin eutectic solder at the peripheral edge. The via-in-cavity structure is designed in the cap substrate, with vertical via holes fabricated and fully electroplated with copper. The detailed design and fabrication technology of this new type of hermetically sealed package are presented with process flow. The performance evaluation and reliability results of a hermetic package will also be presented. The developed wafer-level hermetic package technology is able to fulfill today's requirements for hermetic and cost-effective packaging of high-speed RF-MEMS applications.

Design and optimization of thermo-mechanical reliability in wafer level packaging

In this paper, a variety of wafer level packaging (WLP) structures, including both fan-in and fan-out WLPs, are investigated for solder joint thermo-mechanical reliability performance, from a structural design point of view. The effects of redistribution layer (RDL), bump structural design/material selection, polymer-cored ball application, and PCB design/material selection are studied. The investigation focuses on four different WLP technologies: standard WLP (ball on I/O WLP), ball on polymer WLP without under bump metallurgy (UBM) layer, ball on polymer WLP with UBM layer, and encapsulated copper post WLP. Ball on I/O WLP, in which solder balls are directly attached to the metal pads on silicon wafer, is used as a benchmark for the analysis. 3-D finite element modeling is performed to investigate the effects of WLP structures, UBM layer, polymer film material properties (in ball on polymer WLP), and encapsulated epoxy material properties (in copper post WLP). Both ball on polymer and copper post WLPs have shown great reliability improvement in thermal cycling. For ball on polymer WLP structures, polymer film between silicon and solder balls creates a ‘cushion’ effect to reduce the stresses in solder joints. Such cushion effect can be achieved either by an extremely compliant film or a ‘hard’ film with a large coefficient of thermal expansion. Encapsulated copper post WLP shows the best thermo-mechanical performance among the four WLP structures. Furthermore, for a fan-out WLP, it has been found that the critical solder balls are the outermost solder balls under die-area, where the maximum thermal mismatch takes place. In a fan-out WLP package, chip size, other than package size, determines the limit of solder joint reliability. This paper also discusses the polymer-cored solder ball applications to enhance thermo-mechanical reliability of solder joints. Finally, both experimental and finite element analysis have demonstrated that making corner balls non-electrically connected can greatly improve the WLP thermo-mechanical reliability.

Low temperature wafer level packaging technology of bulk-micromachined MEMS device

New low temperature, low cost, small size packaging technology of novel bulk-micromachined MEMS sensor for mobile applications was developed. The sensor was fabricated with the bulk-micromachining process of SOI substrates and composed with a proof mass, membrane and electrodes for capacitance sensing. The sensor device was capped with very thin (130um-thickness) top and bottom silicon cap wafers which have a 80um-depth cavity. Top and bottom cap wafers were bonded with the sensor wafer with a low temperature curing polymer adhesive lower than 200°C. It is needed that the low temperature packaging technology and the passivation of top and bottom sides of the sensor for keeping the sensor performances and preventing stiction of the proof-mass during the molding processes. After bonding the three substrates, the top cap silicon was dry etched to expose bonding pads for the signal interconnection. The ASIC chip was polished to 75um-thickness, diced and bonded on a half-etched 200um-thick lead-frame with a DAF. The diced wafer-level-capped sensor was stacked on the ASIC, wire bonding was accomplished between the sensor and the ASIC, and the ASIC and the lead-frame and finally transfer molding process was done. The developed package is 24-leads QFN and the dimension is 4.0mm×4.0mm×1.1/1.2mm.

Wafer Level Packaging Technology for Optical Imaging Sensors

Moore’s Law postulated that the number of transistors per chip would double roughly every 2 years. In parallel with the increased device density within a chip, there is an increased overall functionality. This trend can be seen in applications such as MEMS, RF circuits, where sensors, microactuators are integrated with digital and analog electronic components. This complexity leads to smaller bond pads on devices and packaging challenges. One of the requirements for the packages of image sensors and MEMS devices (such as RF- and AeroMEMS) or solar cells is the backside contact. The optical devices require an interface with environment without any restriction caused by the packages and on the other hand require a protection against the environment. Figure 1 shows main differences between IC package and package of an imaging sensor. In this paper, we discuss the two existing wafer-level-packaging technologies used already in mass production and give process details about our new WLP technology using via contacts between front end pads and redistribution.