Wafer-level packaging and direct interconnection technology based on hybrid bonding and through silicon vias

Abstract

The presented wafer-level packaging technology enables the direct integration of electrical interconnects during low-temperature wafer bonding of a cap substrate featuring through silicon vias (TSVs) onto a MEMS device wafer. The hybrid bonding process is based on hydrophilic direct bonding of plasma-activated Si/SiO2 surfaces and the simultaneous interconnection of the device metallization layers with Cu TSVs by transient liquid phase (TLP) bonding of ultra-thin AuSn connects. The direct bond enables precise geometry definition between device and cap substrate, whereas the TLP bonding does not require a planarization of the interconnect metallization before bonding. The complete process flow is successfully validated and the fabricated devices’ characterization evidenced ohmic interconnects without interfacial voids in the TLP bond.