Wafer Level Packaging Technology Research Articles

High-Q Ku-band Microstrip Spiral Resonator in Fan-out Wafer-Level Packaging (FoWLP) Technology for VCO Applications

In this paper, a planar spiral resonator operating at 13 GHz is investigated. The resonator was fabricated using fan-out wafer level packaging (FoWLP) technology. The field analysis highlights the importance of via fence. Two thick film resistors suppress an undesired resonance in proximity of targeted one. The measurements demonstrate a very good correlation in comparison with full-wave simulations. The measured Q-factor defined based on analysis of feedback oscillatory system is about 48. The proposed configuration is suitable for voltage-controlled oscillators (VCOs) with a resonator realized in package.

Characterizations for eWLB (Embedded Wafer Level Ball Grid Array) Antenna in Molded Package Integrations in 77GHz Automotive Applications

The worldwide IC market has had a significant growth rate in recent years, driving diversified package solutions in the segments of communication, computing, consumer, automotive, industrial, etc. Among these market segments, the automotive market is forecast to have the strongest CAGR (Compound Annual Growth Rate) of any of the end-use segments in the next 5 years, which results in more IC packages and components being designed into automotive vehicle systems such as infotainment, ADAS (Advance Driving Assistance System), instrumentation, body systems, battery control systems and so on. In these applications, the 77GHz short-range radar sensor application that can enable higher EIRP (Effective Isotropic Radiated Power) and adaptive cruise control performance has become more attractive to be commercialized. Due to the benefits of shorter interconnection length, lower conductive loss with smooth Cu surface as well as a lower dielectric constant and dielectric loss of materials in a fan-out wafer level package (FOWLP) technology, the FOWLP is proven as a suitable packaging solution to achieve the high speed and frequency requirements in 5G and mmWave applications. The eWLB Embedded Wafer Level Ball Grid Array) is a versatile FOWLP technology, providing a robust package platform in a space-efficient design with the very dense interconnection and routing of multiple dies as well as a smaller footprint and lower package profile providing a reliable package solution. Meanwhile, since the utilization of an antenna that is integrated into the packages has been studied as a lowcost solution because the packages can be tested in normal FR4 printed circuit board (PCB) instead of the RF function integrated PCB, the eWLB integrated with molded antenna chip packages (called eWLB antenna in molded package) technology is introduced in this paper. The characterizations for assembly process challenges are evaluated and illustrate the process optimizations of equipment handling, antenna molded chip package fabrication, reconstitution process control and warpage characterization of the molded wafer. In addition, the radio frequency (RF) test validation is performed to verify the performance of scattering parameter (S-parameter), radiation pattern, impedance and detection range of the antenna. In order to prove the reliable quality and yield of the evaluated eWLB antenna in molded packages, package-level reliability tests are studied. Through these results, it will show that this eWLB antenna in molded package integration is a robust and costeffective solution for 77GHz automotive applications.

Ultrathin Antenna-in-Package Based on TMV-Embedded FOWLP for 5G mm-Wave Applications

In this paper, a novel through mold via (TMV)-embedded fan-out wafer-level package (FOWLP) technology was demonstrated to manufacture the well-designed Antenna in Package (AiP) with ultrathin thickness (0.04 λ0). Double-sided redistribution layers (RDLs) were employed to build the patch antenna, while a TMV interposer was used to connect the front and back RDLs. By optimizing the AiP’s parameters, the patch antenna can achieve a wide impedance bandwidth of 17.8% from 24.2 to 28.5 GHz, which can cover the 5G frequency bands. Compared with previous works, the proposed AiP has significant benefits in terms of its ultralow profile, easy processing, and high gain. Hence, the TMV-embedded FOWLP should be a promising technology for fifth generation (5G) millimeter wave (mm-Wave) applications.

Investigation of the Processing Behavior and Stability of Different Glass Frit Materials

Although glass frit bonding has long been a well-established process in the industry, research and development efforts are continuously improving it for application in modern MEMS products. First, it should be mentioned that the main advantage of the glass frit bonding is easily integration of this process module into even the most complex technologies. Using screen printing, the glass frit paste can be applied in a structured manner to one of the two wafers to be bonded, no subsequent structuring (e.g., by lithography and etching) is necessary. Subsequently, the paste is transformed into a compact glass in a batch process (the organic binder is burned out in a furnace and the glass particles are melted). The bonding is performed in conventional wafer bonders. The glass frit, which is located as an intermediate layer between the wafers to be bonded, is melted, and joined by surface wetting to form a heretic seal (vacuum or defined gas pressures can be included). During cooling the glass solidifies and forms a very strong and reliable bond. Virtually all surface layers utilized in microsystems technology can be bonded. The surface roughness of the wafers does not play any role here and even rather high topographies (e.g. metal lines in the bond interface) can be well covered and sealed [1]. Related to this process flow, the glass frit bonding is very cost attractive, e.g., compared to Al-Ge eutectic bonding.The research and development activities of the last years, the requirements that led to them and the corresponding solutions are to be presented and discussed here. Bond frame width: screen printing is mostly associated with very coarse and broad structures and in fact a few years ago, the bond frame width determined the chip size. In the meantime, bond frame widths of 100 µm and smaller can be realized, which is hardly larger than with other bonding processes and allows the economical production of small chips. To realize this, special new screen materials are of key importance. Wafer layout of the Glass Frit layer: with the smaller chips, sealing rings at the wafer edge and support structures in the scribe line, the degree of coverage during screen printing increased significantly, which makes the release of the screen and thus a defined printing process much more challenging. These requirements can be achieved with the new screen materials and measures for keeping the back of the printing screen clean. Glass frit in complex manufacturing chains: Glass frit wafer bonding is not only utilized at the very end of the process to encapsulate MEMS structures; it is now also part of complex wafer level packaging technologies for realizing SoC (system on chip) solutions. After wafer bonding, many different process steps are implemented to create through-silicon-vias (TSVs) and solderable metallizations, for example. The above-mentioned sealing rings at the wafer edge are an important requirement for bonded wafers in such processes, in which mainly wet chemicals are used, therefore it is also essential that the glass frit is chemically resistant and thermally stable up to a certain temperature. This was investigated for different glass frit materials, and it can be concluded that there is a good stability against water and solvents. The resistance to bases varies from material to material and acids usually destroy the glass (Figure 1). Regarding the temperature, it can be stated that up to 50 °C below the bonding temperature, the Glass frit can be considered as solid. Lead-free glass frit materials: until now, lead in glass frit materials was exempt from the legal regulations governing their use. These exemptions will expire in the foreseeable future [2]. Therefore, the detailed evaluation of lead-free glass frits is of very high importance. These materials are currently being investigated in terms of the entire process chain in preparation for industrial application. This evaluation faces some challenges (crystallization tendency of lead-free glasses) but also advantages (e.g., significantly low bonding temperatures are possible with Te-based glass solders). Even though glass frit bonding appears at first glance to be a well-understood process that is easy to apply. There are several modern manufacturing processes, with new challenges that can be mastered by understanding the materials and the processes. However, this requires extensive research and optimization.Literature:[1] Knechtel, Roy. "Glass frit bonding: an universal technology for wafer level encapsulation and packaging." Microsystem technologies 12.1-2 (2005): 63-68.[2] DIRECTIVE 2011/65/EU OF THE EUROPEAN PARLIAMENT AND OF THE COUNCIL Figure 1

(Invited) Micro-Transfer-Printing: A Novel Technology for Volume D2W Integration

In the past decade, the semiconductor industry has witnessed an ever-increasing demand in wafer-level integration and packaging technologies driven by increased requirements on functionality, performance, and efficiency. As one of the world’s leading specialty foundry groups for analog/mixed semiconductor technologies and more than thirty years of experience in volume manufacturing for automotive, industrial and medical applications, the X-FAB group has recognized this trend and broadened its offer accordingly. New integration techniques like wafer bonding, through-passivation vias (TSVs) processing, redistribution layers (RDLs) as well as the readiness to introduce new material systems like glass, polymers, noble metals, or compound semiconductors in a CMOS manufacturing environment clearly highlight the ongoing transformation process.Next to the stated, also Die To Wafer (D2W) integration technologies receive an increased interest and represent one additional topic of these developments. Especially the Micro-Transfer-Printing technology (also referred as mass transfer or just transfer-printing) gained particular interest and has seen comprehensive developments over the past years.To enable a heterogeneous chip integration, the micro-transfer-printing technology utilizes elastomeric stamps (see Figure 1 a; gray) with tunable adhesive properties to transfers devices or arrays of devices (commonly referred to as chiplets) from their native substrate (source wafer, orange) to a non-native target material (blue). This integration approach does not only enable heterogeneous 3D-wafer-level integration, it also provides several benefits like: high potential throughput since thousands of chiplets can be transferred in a parallel manner by the elastomeric stamp,the possibility to integrate smallest-scale devices,the opportunity to effectively utilize expensive source wafers and to transfer chiplets to multiple devices or target wafers,the high placement accuracy of 3σ < 1.5 µm, andthe opportunity to package devices with extremely short metallization tracks. To offer this versatile technology, X-FAB has set-up a µTP pilot line for the development and industrialization of related processes in the MEMS clean room facilities in Erfurt, Germany.Enabling an integration as depicted in Figure 1a) requires the development of several dedicated process sequences that have to be applied to source (orange) and target wafer (blue) to: form chiplets that are appropriate for integration via µTP, i.e. the source wafer has to be made “print-ready”,enable a high adhesion and thereby high print yield by adding a dedicated adhesion layer on the target wafer, andallow wiring and passivation of the integrated devices by subsequent adhesion patterning, redistribution layer (RDL) formation and passivation layer deposition. Out of the variety of potential integration option and material systems, X-FAB decided to focus on basically two integration scenarios, namely i) the preparation of print-ready SOI-based CMOS ASICs and ii) heterogeneous integration on CMOS wafers which both shall be explained in more detail within this presentation.The general process to make devices print-ready involves the chiplet singulation by multiple dry etches to form trenches down to handle wafer bulk material,the tether formation by SixNy deposition and patterning to form a mechanical system that holds the chiplet in place andthe wet chemical release etch to separate the singulated µIC from the handle wafer. Thereby, a print-ready µASIC is formed. It refers to a state in which the IC is separated from its original handle wafer and just kept in place by the tether systems as shown in Figure 1b. A basic requirement for the development of this process is the use of an SOI technology (such as X-FAB’s XT018), since the buried oxide layer (BOX) acts as the chiplet bottom protection in the final release etch.Next to the scope of providing X-FAB’s µASICs for an integration via transfer-printing, X-FAB is actively working on the assembly of III/V semiconductor elements/chiplets on CMOS ICs/ wafers to improve the performance of the available CMOS devices or even add new functionality. Based on the availability of print-ready III/V semiconductor chiplets provided by X-FAB’s foundry partners, the integration process involves the deposition of an adhesive layer on top of the CMOS wafer surface,the transfer-printing integration of the III/V chiplets,the final curing of the adhesive layer to adjust the material properties,the patterning of the adhesive by a dry etching process to open the CMOS wafer contact pads,the subsequent formation of a copper redistribution layer (RDL) andfinally, the passivation of the formed wafer-level package to protect the integrated chiplet and the metallization layer from environmental influences. An example of such an integrated wafer-level package (without passivation) is illustrated in Figure 1 c). Figure 1

A Wideband Co-Linearly Polarized Full-Duplex Antenna-in-Package With High Isolation for Integrated Sensing and Communication

In this letter, a novel co-linearly polarized full-duplex antenna-in-package (AiP) with high Tx/Rx isolation and wide decoupled bandwidth is proposed for integrated sensing and communication (ISAC). Fan-out wafer-level packaging technology is employed, and the preparation process is discussed in details. To improve Tx/Rx isolation, the current direction of the patch elements is orthogonal to that of the feeding ports. Two identical 1×2 patch antenna arrays are used as Tx and Rx antennas, respectively. To further suppress mutual coupling, a decoupling loop is proposed to enhance Tx/Rx isolation. In addition, a wideband full-duplex AiP with high isolation and wide decoupled bandwidth is also proposed by using the parasitic technique and the proposed decoupling method. Prototypes are fabricated and measured to verify the proposed AiPs. The measurement results demonstrate that the proposed AiP possesses the merits of high Tx/Rx isolation (up to 53 dB), wide isolation bandwidth (up to 9.2%) and low cost, providing a foundation for chip-level applications in ISAC.

Development and Characterization of Low Temperature Wafer-Level Vacuum Packaging Using Cu-Sn Bonding and Nanomultilayer Getter.

Most microsensors are composed of devices and covers. Due to the complicated structure of the cover and various other requirements, it difficult to use wafer-level packaging with such microsensors. In particular, for monolithic microsensors combined with read-out ICs, the available process margins are further reduced due to the thermal and mechanical effects applied to IC wafers during the packaging process. This research proposes a low-temperature, wafer-level vacuum packaging technology based on Cu-Sn bonding and nano-multilayer getter materials for use with microbolometers. In Cu-Sn bonding, the Cu/Cu3Sn/Cu microstructure required to ensure reliability can be obtained by optimizing the bonding temperature, pressure, and time. The Zr-Ti-Ru based nanomultilayer getter coating inside the cap wafer with high step height has been improved by self-aligned shadow masking. The device pad, composed of bonded wafer, was opened by wafer grinding, and the thermoelectrical properties were evaluated at the wafer-level. The bonding strength and vacuum level were characterized by a shear test and thermoelectrical test using microbolometer test pixels. The vacuum level of the packaged samples showed very narrow distribution near 50 mTorr. This wafer-level packaging platform could be very useful for sensor development whereby high reliability and excellent mechanical/optical performance are both required. Due to its reliability and the low material cost and bonding temperature, this wafer-based packaging approach is suitable for commercial applications.

A K-Band Hybrid-Packaged Temperature-Compensated Phased-Array Receiver and Integrated Antenna Array

This article presents an eight-channel 1.9-dB noise figure (NF) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$K$ </tex-math></inline-formula> -band phased-array receiver (RX) for satellite communication (SATCOM). It employs the hybrid-packaged 65-nm CMOS beamformer and 0.1- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> GaAs low-noise amplifiers (LNAs) based on the fan-out wafer-level chip-scale packaging (WLCSP) technology. For the power-efficient RX implementation, the power consumption of gain and phase tuning blocks is discussed, and the fully passive phase shifter (PS) and attenuator (ATT) are employed in this work. A global biasing scheme is proposed to ensure performance uniformity across temperature variations. Across the SATCOM band of 17.7–20.2 GHz, the proposed hybrid-packaged phased-array RX IC only consumes 30.2-mW dc power per channel and achieves < 1.2-dB gain variation and < 0.9-dB NF variation from −40° to 85 °C. Based on the RX IC, a dual-polarized 1024-element RX antenna array is further introduced. The measured gain-to-noise temperature ratios (G/Ts) are 6.22 and 6.51 dB/K at 19.7 GHz for left- and right-hand circular polarizations, respectively.

A Novel Packaged Ultra-High Q Silicon MEMS Butterfly Vibratory Gyroscope.

A novel three-dimensional (3D) wafer-level sandwich packaging technology is here applied in the dual mass MEMS butterfly vibratory gyroscope (BFVG) to achieve ultra-high Q factor. A GIS (glass in silicon) composite substrate with glass as the main body and low-resistance silicon column as the vertical lead is processed by glass reflow technology, which effectively avoids air leakage caused by thermal stress mismatch. Sputter getter material is used on the glass cap to further improve the vacuum degree. The Silicon-On-Insulator (SOI) gyroscope structure is sandwiched between the composite substrate and glass cap to realize vertical electrical interconnection by high-vacuum anodic bonding. The Q factors of drive and sense modes in BFVG measured by the self-developed double closed-loop circuit system are significantly improved to 8.628 times and 2.779 times higher than those of the traditional ceramic shell package. The experimental results of the processed gyroscope also demonstrate a high resolution of 0.1°/s, the scale factor of 1.302 mV/(°/s), and nonlinearity of 558 ppm in the full-scale range of ±1800°/s. By calculating the Allen variance, we obtained the angular random walk (ARW) of 1.281°/√h and low bias instability (BI) of 9.789°/h. The process error makes the actual drive and sense frequency of the gyroscope deviate by 8.989% and 5.367% compared with the simulation.

(Invited) Fan-out Wafer-Level Packaging: Opportunities and Challenges Towards Heterogeneous Systems

This article describes opportunities and challenges towards heterogeneous systems integration by the so-called fan-out wafer-level packaging (FOWLP) technology. An introduction on the technology is given, before we describe specific developments built up at CEA-Leti. Recent assessments of a multi-chip SiP for 5G applications and scalable three-dimensional interconnects are presented.

Suppression strategy for process-induced warpage of novel fan-out wafer level packaging

In the study, the novel fan-out wafer level packaging (FOWLP) technology is presented in which the through silicon via (TSV) array interposer layer is manufactured. Compared to conventional FOWLP technology, the present novel FOWLP technology has several advantages of better signal integrity, higher electrical performance, and easier customization. However, similar to the conventional FOWLP technology, the process-induced warpage resulted from the mismatch of the coefficient of thermal expansion (CTE) among the constituent materials is also an essential issue during the fan-out fabrication process, which is notably for successful process integration. This study proposes a comprehensive assessment of the process-induced warpage of the novel FOWLP during the fan-out fabrication process. A process-dependent simulation methodology is introduced, which integrates nonlinear finite element (FE) analysis incorporated with the element death-birth technique. The study starts from establishing a silicon interposer layer with TSV array, attachment of glass carrier, multiple redistribution layers (RDLs), and dielectric layers. The warpage evolution during the fan-out fabrication process is thoroughly evaluated according to the temperature loading profile. To demonstrate the effectiveness of the proposed theoretical model, the novel FOWLP test vehicle is manufactured for experimental measurement. Finally, the parametric study together with response surface methodology is further applied to provide guidelines for suppressing the warpage. Overall, the simulation modeling represents a feasible approach for predicting the process-induced warpage during the fan-out fabrication process.

Development of a Reliable High-Performance WLP for a SAW Device.

In this paper, we present wafer-level packaging technology for surface acoustic wave (SAW) filters with higher long-term reliability and better electrical performance. This article focuses on the package structure, fabrication processes, and reliability for the SAW filter wafer-level package (WLP). The key processes, including cavity wall (CW) dam formation through non-photosensitive film vias development using a laser drilling process, a redistribution layer (RDL), and ball-grid array formation are developed. In addition, a numerical study based on the finite element model has been conducted to analyze the stress distribution of Cu RDL traces. In addition, the CW dam and the roof layer are covered with polymer, which solves the delamination problem between the CW dam and the substrate. Meanwhile, after practical verification, the SAW filter WLP was resistant to encapsulating pressure using a high elastic modulus capping material, which solved the collapse problem. Additionally, a comparison of the RF filter package’s electrical performance following the preconditional level 3 and unbiased highly accelerated stress test revealed no differences in insertion attenuation across the passband (<0.2 dB, standard value: 1 dB). The final packages passed the reliability tests in the field of consumer electronics.

Two-Mask Wafer-Level Vacuum Packaging With Bulk-Si 3D Interconnects for MEMS Devices and Its Package Performances

We present the novel 3D wafer-level vacuum packaging technology for MEMS, which only needs two masks and is realized by Au-Si eutectic bonding with a low-resistivity Si Cap wafer. Wherein, Au-Si bonding pads and rings are formed to accomplish vertical interconnects and a vacuum package respectively. Applied to resonators with two typical substrate wafers of Si and Glass, this 3D package structure has further gone through the systemic characterizations. Specifically, the high-reliable mechanic strengths of device packages are revealed from Au-Si bonding strengths measured as about 20 MPa in tensile tests. Based on analyzing parasitic capacitance networks in device packages, the feed-through effect in resonance tests can be effectively relieved by grounding on each Si layer in device package structures (i.e. the parasitic capacitance reduced from the level of pF to fF). By resonance tests, it is found that increasing the degassing duration (30 min <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\to 60$ </tex-math></inline-formula> min <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\to 100$ </tex-math></inline-formula> min) is beneficial for improving package vacuum degrees as well as consistencies (69% within 4–30 kPa <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\to 88$ </tex-math></inline-formula> % within 0.6-1.2 kPa <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\to 85$ </tex-math></inline-formula> % within 0.6-0.8 kPa), and hermetic package yields (73% <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\to 86$ </tex-math></inline-formula> % <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\to 100$ </tex-math></inline-formula> %). Besides, device packages are verified to have good long-term stability by monitoring quality factor variations in 6 months. Overall, this proposed 3D packaging technology has extensive application prospects in various MEMS devices due to its inherently-simple process, low capacitive feed-through effect, and fine package performances. Also, test results provide instructions on the realization of low-parasitic-capacitance signal interfaces and the optimization of wafer-level vacuum package processes.

A 1.9-dB NF K-Band Temperature-Healing Phased-Array Receiver Employing Hybrid Packaged 65-nm CMOS Beamformer and 0.1-μm GaAs LNAs

A 1.9-dB NF K-band phased-array receiver (RX) is presented, which employs the hybrid packaged 65-nm CMOS beamformer and 0.1- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> GaAs LNAs based on the fan-out wafer-level chip-scale packaging (WLCSP) technology. Power-efficient gain and phase tuning blocks are utilized to reduce power consumption. Temperature-healing design methodology is adopted to ensure nearly constant gain response versus temperature variations. The proposed phased-array RX only consumes 30.2-mW dc power per channel and achieves < 1.2-dB gain variation and < 0.9-dB NF variation from −40 °C to 85 °C.

Experimental and Numerical Investigations of the Warpage of Fan-Out Wafer-Level Packaging With SAW Filters

Fan-out wafer-level package (FOWLP) technology is an ideal scheme for the surface acoustic wave (SAW) filter packaging due to its potential to achieve extensive numbers of interconnects with standard pitches at any shrink pattern of the wafer. Nevertheless, predicting the wafer warpage in the processes timeline is an intractable but instructive issue. This article focuses on the evolution of the wafer warpage in different packaging processes and on ameliorating the warpage control scheme for the FOWLP with the (SAW) filters. Combined with the meso-mechanical model and the transversely isotropic model (TIM) of composite material, curing deformation is taken into account. Given the anisotropy coefficient thermal expansion (CTE) of the LiTaO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> , experiments and simulations are performed to analyze the influence of the process, structure, and material effects on the warpage. In addition, a new experimental process is proposed to reduce the impact of significant mismatches with submillimeter dies. Compared with the theoretical simulations, a class of warpage tests performed are achieved consensus. Finally, the warpage of the 8-in wafer is controlled within 2 mm.

Wafer-Level Assembly of Physics Package for Chip-Scale Atomic Clocks

Chip-scale atomic clocks (CSACs) have been extensively investigated and many prototypes or products have been realized as time sensors. Researchers focus on improving the frequency stability performance, reducing the volume and the power consumption of CSACs. To the best of our knowledge, the physics packages reported until now are all assembled from discrete components. This traditional assembly method has a very low efficiency and causes variations among different physics packages. In this article, we propose a wafer-level assembled physics package for CSACs based on three dimensional (3-D) wafer-level packaging (WLP) and microelectromechanical system (MEMS) technologies. The components of the physics package are all fabricated on wafers. These wafers are integrated together vertically and then diced into separate physics packages. The proposed method has the advantages of high uniformity among different physics packages and high efficiency. And it improves the utilization rate of wafers by reducing the unused area. Thus, the production cost is reduced considerably. The volume of the proposed functional physics package is less than 8 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> . The prototype chip-scale atomic clock incorporating the proposed physics package reveals the coherent population trapping (CPT) linewidth of 1.8 kHz and the total power consumption of about 20mW. The frequency stability is about <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6.1 \times 10^{-12}$ </tex-math></inline-formula> @1000s. The observed results demonstrate promising performance of the wafer-level assembled physics package. The approach described in this article reveals a viable method for batch production for its low cost, high efficiency and high product uniformity.

A micro-thin-film getter–heater unit for high vacuum capsulation of MEMS devices

In this paper, we proposed a micro-getter unit with a square thin-film getter formed atop a thin-film heater for vacuum packaging of a Micro-Electro-Mechanical System (MEMS) device. This innovation through an integrated module unit can be fabricated by MEMS compatible processes and can be sealed together with a MEMS device by wafer level package technology sequentially. It has the advantage of locally and repeatedly activating the getter by supplying a DC power to the micro-thin-film heater. Two models have been studied comparatively in this work, in which a conventional solid structure (SS) model with a micro-heater directly above a silica glass substrate was used as a reference model for comparison with the newly designed innovative floating structure (FS) model with a micro-heater floating over a cavity in a silicon substrate. According to a finite element method simulation based on Fourier’s law of heat conduction, the FS model showed better thermal efficiency than the SS model during the activation process. For a square micron thin-film getter with a size as 1000 × 1000 × 5 µm3, a rather low input voltage as 2 V can raise the temperature of the getter up to 300 °C calculated by the FS Model, while the SS model requires a much higher input voltage as 18 V to reach the same temperature.

Fabrication and high-frequency characterization of low-cost fan-in/out WLP technology with RDL for 2.5D/3D heterogeneous integration

Redistribution layer (RDL) and through silicon via (TSV) are the two main important packaging methods of the heterogeneous integration, here we report on the interconnection characteristics in Fan-in/out wafer level packaging (WLP) technology with three RDLs for 2.5-D/3-D heterogeneous integration where a 12-in wafer with medium silicon resistivity was used to reduce the cost of per unit area. Different structures of the interconnections line with different location of metal layer, such as coplanar waveguide, microstrip line and strip line, are designed to determine the material parameters in this technology. The determined material parameters can help designers achieving the desired devices’ performance without multiple iterations, thereby greatly reducing the design cost. The effect of the location of the interconnection lines are also discussed in this paper. A process design kit (PDK) with the verified material parameters is proposed and used to design passive components, such as spiral inductor and hairpin filters, resulting in good agreement between simulated data and the measured data, which further proves the reliability of PDK. The frequency ranges (up to 110 GHz) of the hairpin filters also indicate a wide application range of the PDK proposed here.

Warpage Analysis and Prediction of the Advanced Fan-Out Technology Based on Process Mechanics

Moore’s law has remarkably promoted the development of semiconductor technology over the last decades. The advanced packaging involving novel materials, structures, and processes has contributed significantly to achieving excellent performance. Among various forms of advanced packaging, wafer-level-fan-out packaging is superior to standard wafer-level packaging in that it allows more input/output (I/O) connections, leading to landmark development for high-end devices. Furthermore, fan-out wafer-level package (FOWLP) technology enables heterogeneous integration of chiplets fabricated with different manufacturing processes, which provides integrated, sophisticated, and multifunctional dies with higher performance, lower cost, and tinier size. In packaging materials, processes, and structures, a thorough understanding of the process mechanics is necessary to ensure accuracy, while multiphysical field and multiscale modeling are beneficial to clarifying the internal mechanism of warpage. Process mechanics was applied to FOWLP and the characteristics were systematically expounded. Focusing on the warpage analysis of the embedded silicon fan-out (FO) wafer-level package, we introduced the principle of process mechanics and explored the material–structure–process interaction. The typical processes (including: 1) cleaning and litho cavity; 2) die attach and assignment; 3) dry film and dielectric layer 1 and patterning; 4) physical vapor deposition (PVD) seed layer 1 and patterning copper plating and redistribution layer (RDL) 1; 5) dielectric layer 2 and patterning; 6) PVD seed layer 2 and patterning copper plating and RDL 2; and 7) passivation layer, drop ball back grinding, and dicing) of the embedded silicon FO packaging are analyzed in detail to explore the warping evolution of individual processes. In addition, a material equivalent model of representative volume element (RVE) and an extended theoretical model of a multilayer structure were proposed. The comprehensive comparison for the extended theoretical model, experimental measurement, and finite element model (FEM) showed that the theoretical model is effective and relatively accurate. Overall, both the theoretical model and FEM are feasible approaches for predicting the warpage during the manufacturing process.

Photonic Debonding for Wafer-Level Packaging

Abstract Temporary bonding and debonding (TB/DB) processes have emerged as promising solutions in wafer-level packaging technology. These processes offer a pathway to wafer thinning and subsequent backside processing, which are crucial in enabling heterogenous integration using technologies such as 3D through-silicon-vias (TSVs) and fan-out wafer-level packaging. These are critical for overall device miniaturization and increased performance. In this work, a novel photonic debonding (PDB) method and the corresponding bonding material are presented. PDB enhances the TB/DB process by overcoming many of the disadvantages associated with traditional debonding methods. PDB uses pulsed broadband light (200 nm – 1100 nm) from flashlamps to debond temporarily bonded wafer pairs with glass as the carrier wafer. These flashlamps generate high-intensity pulses of light (up to 45 kW/cm2) over short time intervals (~100 μs) to facilitate the debonding. Feasibility of the PDB in the TB/DB process is demonstrated by successfully debonding thinned (&amp;lt;70 μm) silicon wafers from glass carriers. Post-debond cleaning of the thinned wafers and carriers is evaluated. With uniform, large-area illumination (75 mm x 150 mm) per flashlamp and with the ability to concatenate lamps to increase the illumination area of the PDB tool, the PDB method offers a high-throughput and low-cost debonding solution for both wafer-level and panel-level packaging technologies.