Wafer-level Measurement Research Articles

Deep learning-based data processing method for transient thermoreflectance measurements

Pump–probe thermoreflectance has been commonly applied for characterizing the thermal properties of materials. Generally, a reliable and efficient non-linear fitting process is often implemented to extract unknown thermal parameters during the pump–probe thermoreflectance characterizations. However, when it comes to processing large amounts of data acquired from similar structural samples, non-linear fitting process appears to be very time-consuming and labor-intensive to search for the best fitting for every testing curve. Herein, we propose to apply deep learning (DL) approach to nanosecond transient thermoreflectance technique for high-throughput experimental data processing. We first investigated the effect of training set parameters (density and bounds) on the predictive performance of the DL model, providing a guidance to optimize the DL model. Then, the DL model is further verified in the measurement of the bulk sapphire, SiC, diamond samples, and GaN-based multilayer structures, demonstrating its capability of analyzing the results with high accuracy. Compared to the conventional non-linear fitting method (such as Global Optimization), the computation time of the new model is 1000 times lower. Such a data-driven DL model enables the faster inference and stronger fitting capabilities and is particularly efficient and effective in processing data acquired from wafer-level measurements with similar material structures.

The Ferris ferromagnetic resonance technique: Principles and applications

Measurements of ferromagnetic resonance (FMR) are pivotal to modern magnetism and spintronics. Recently, we reported on the Ferris FMR technique, which relies on large-amplitude modulation of the externally applied magnetic field. It was shown to benefit from high sensitivity while being broadband. The Ferris FMR also expanded the resonance linewidth such that the sensitivity to spin currents was enhanced as well. Eventually, the spin Hall angle (θSH) was measurable even in wafer-level measurements that require low current densities to reduce the Joule heating. Despite the various advantages, analysis of the Ferris FMR response is limited to numerical modeling, where the linewidth depends on multiple factors such as the field modulation profile and the magnetization saturation. Here, we describe, in detail, the basic principles of operation of the Ferris FMR and discuss its applicability and engineering considerations. We demonstrated these principles in a measurement of the orbital Hall effect taking place in Cu using an Au layer as the orbital-to-spin current converter. This illustrates the potential of the Ferris FMR for the future development of spintronics technology.

Quantitative analysis of irregular channel shape effects on charge-trapping efficiency using massive 3D NAND data

The randomly fluctuating trap efficiency of taper-etched nanowire thin-film transistors was investigated by measuring a very large statistical ensemble of three-dimensional NAND flash memory cells. We made trapping in n-bit multi-level cells using incremental step pulse programming and observed the widening of the threshold voltage distribution caused by abnormal program cells. Further, we classified the components that broaden the threshold voltage distribution in both chip- and wafer-level measurements to analyze behaviors of the randomly fluctuating abnormal program cell. The variations in reading and programming operations are difficult to separate because they act simultaneously in the data reading and writing operations. For each pulse of the programming, the variations occur in reading for verification, in programming itself, and in reading after program completion. To analyze the inseparable variation, we used a method to extract only the intrinsic over-programming by removing variations in the read operation from the entire abnormal program cell. Using this extraction method, we could distinguish between the simultaneous read variation and over-programming. In particular, the unpredictable effect of the three-dimensional structure, such as the irregular shape and different radius due to the tapered channel hole profile from the nonideal etching process, was calculated and verified using experimental data. We quantitatively analyzed the experimental data one by one for each cell within the entire distribution, and each pulse of dozens in the programming scheme. This analysis provides quantitative information on the variations in charge-trapping efficiency and the threshold voltage distribution width by irregular-shaped tunneling layers.

Evaluation of Chip-Package Interaction by Means of Stress Sensors

In this study, the chip-package interaction is analyzed by means of stress sensors with electrical simulation being initially carried out to optimize the stress sensor model. The analysis includes determination of piezoresistive coefficients along with a systematic characterization approach, starting with wafer-level measurements and finalizing with package-level measurements. Final validation is carried out using a ceramic package, where the electrical measurements fully confirm the results from mechanical simulations and thus verify the suggested proof-of-concept. Besides obtaining valuable information on the piezoresistive coefficients and validating the evaluation approach, this study also generates a guideline: in a phenomenological manner we show which mechanisms and effects need to be taken into account to provide reliable evaluation of stress distribution in a semiconductor package by using stress sensors.

Evaluation of the impact of abnormal grains on the performance of Sc0.15Al0.85N-based BAW resonators and filters

Sc x Al1−x N is a promising piezoelectric material for radio frequency communication applications with excellent electro-acoustic properties. However, the growth of abnormally oriented grains is widely observed in the Sc doped AlN films deposited by sputtering. In this work, for the first time, the impact of the abnormal grains in the Sc0.15Al0.85N films on the performance of bulk acoustic wave resonators and filters is systematically evaluated by both simulations and measurements. The correlation between the device performance and the abnormal grain parameters, including the density, dimension, crystal orientation, growth height and the total volume of the abnormal grains, is evaluated and quantified. Simulation results show that the total volume of all abnormal grains in the whole device is the most critical factor among the parameters. Abnormal grains with randomly distributed parameters and around 6% total volume of the film can degrade the effective coupling coefficient of the resonator from 13.6% to 11%, leading to a 10.6% decrement of the filter bandwidth. Wafer-level device characterizations and measurements are performed, and the results are consistent with the simulations. This study provides a practical method for predicting the performance of the resonators and filters with abnormal grains, and a guideline for film quality evaluation.

(Invited) Understanding Self-Heating in FinFETS and Its Impact on Metal Interconnect

Self-Heating (SE) in FinFETs can be of significant concern for reliability of back-end-of-line (BEOL) interconnects due to electromigration (FM) failure, which is a highly sensitive degradation mechanism at elevated temperatures (1, 2). Temperature levels of ≥5°C due to front-end-of-line (FEOL) self-heating at M1 lines can impact the circuit’s reliable operation (3). The confined heat due to self-heating in FinFETS can flow vertically and laterally to the local interconnects and increasing the metal temperature thereby accelerating the EM failure rate probability. Furthermore, while FinFETs provide the performance, power and scaling advantages over planar devices the local self-heating can potentially affect device performance and exacerbate the effects of various reliability mechanisms (4). It is, therefore, imperative to understand the quantification of self-heating in FinFETs and its reliability implications in the devices, circuits and metal interconnects.In this presentation we will discuss several experimental methodologies to quantify SH using wafer level measurements by implementing three different types of electrical sense elements. The sensing schemes evaluate the surround heat sensing using the electrical characteristic of a neighboring FET device and a local heat sensing element using a 4-terminal kelvin contact to measure the thermal coefficient of resistance of the metal gate. We will evaluate the proximity and effectiveness of these sense elements. We will also investigate the impact of SH on logic circuits using a simple ring-oscillator circuit. The characteristics will be validated through predictive thermal simulations. From the results it is inferred that dense circuit applications such as clock buffers are required to be studied more carefully for its impact of self-heating on upper metal lines. This is particularly critical for technologies such as SOI FinFETs where heat generated by frontend-of-line devices is being forced through the upper metal lines due to the buried oxide where self-heating impact is 5x higher compared to bulk FinFET technology.The author acknowledges the collaborators of Globalfoundries, especially Dr. Peter Paliwoda, for the technical discussion.References W. Chang, S.E. Liu, B.L. Lin, C.C. Chiu, Y.-H. Lee and K. Wu, IEEE IRPS, 2F.6.1, (2015).S-W. Yoo, H. Kim, M. Kang, and H. Shin, of Semicon. Tech and Sc, vol.16(2), 204, (2016).Peter Paliwoda, Doctoral Dissertation, https://digitalcommons.njit.edu/dissertations/1389, NJIT, 1389, pp. 96, (2018).Paliwoda, Z. Chbili, A. Kerber, T. Nigam, K. Nagahiro, S. Cimino, M. Toledano-Luque, L. Pantisano, B.W. Min, and D. Misra, IEEE Trans. on Dev. and Mat. Reliability, vol. 19(2) (2019).

Hot electron effects in AlGaN/GaN HEMTs during hard-switching events

This work contains an investigation of hot-electrons effects in GaN transistors during a hard-switching event by means of wafer-level measurements and TCAD mixed-mode hydrodynamic simulations. The latter reveals the presence of hot electrons at the passivation/barrier interface during commutation. Trapping in this location can explain the measured on-state resistance increase during switching operation and leads to a redistribution of the lateral electric field in the two-dimensional electron gas, which in return modulates the hot electron injection process.

Cryogenic temperature DC-IV measurements and compact modeling of n-channel bulk FinFETs with 3–4 nm wide fins and 20 nm gate length for quantum computing applications

CMOS circuits for Quantum Computing applications require FETs operating at cryogenic temperatures. In this work, we aim to present one of the first insights on the ability of the industry standard compact model BSIMCMG in capturing low temperature device physics. We have performed wafer-level DC-IV measurements on multi-fin n- channel bulk FinFETs with 3–4 nm wide fins and down to 20 nm designed gate length across a range of temperatures spanning from 393 K down to 4 K. Our initial results show that while our model to hardware correlation at room temperature is acceptable, at cryogenic temperatures the model may need improvement, especially in the saturation region of the device operation.

Resonances on GaN-on-Si Epitaxies: A Source of Output Capacitance Losses in Power HEMTs

GaN-on-Si high-electron-mobility transistors (HEMTs) exhibit excellent properties for efficient power conversion. Nevertheless, a considerable energy loss associated with the charging and discharging of the output capacitance ( C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OSS</sub> ) in these transistors severely limits their application at high switching frequencies. In this work we report the observation of unexpected resonances in GaN-on-Si HEMTs. These high-frequency resonances lead to considerable energy losses in fast charging and discharging of the C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OSS</sub> during switching transients. We propose a simple wafer-level measurement technique to evaluate such losses at the epitaxy level, prior to the transistor fabrication. Experimental results from this technique revealed that the Silicon substrate is the main origin of these losses. Such wafer-level evaluation of C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> OSS</sub> losses opens opportunities to characterize and optimize epitaxies for future power devices, especially those operating at high switching frequencies.

Frequency Induced Stiction for MEMS Accelerometers

With the rising market for inertial MEMS, reliable stiction detection methods at wafer level become increasingly important. This paper describes a new mechanism for producing enhanced stiction results at wafer level testing due to electric stimulation of the electrode fingers of the MEMS devices and provides a new wafer level measurement method to detect critical frequency ranges. Dependent on the architecture of the sensor core the modulation frequency and amplitude have a distinct impact on the stiction results. The effect is studied systematically for two different test device types by variation of the modulation carrier amplitude and frequency. The results are compared to critical modes gained from transient finite element simulations of the sensor cores. Additionally, a mechanical modal analysis has been performed for result verification. The obtained results show a distinct correlation between the resonance frequencies of the electrode fingers and the likelihood of stiction events. [2019-0189]

Development of Six-Degree-of-Freedom Inertial Sensors With an 8-in Advanced MEMS Fabrication Platform

This paper presents the development of an 8-in six-degree-of-freedom (DOF) inertial sensor based on an advanced capacitive inertial sensor fabrication platform. The platform integrates three-axis gyroscopes and three-axis accelerometers on the same chip. The fabricated sensors are vacuum packaged at the wafer level with a polysilicon-based through-silicon interposer (TSI) using the aluminum-germanium eutectic bonding approach. Waferlevel measurement results indicate that a fabrication yield of greater than 92% and a vacuum level of ~100 mtorr have been achieved. The fabricated inertial sensors and the customized application-specific integrated circuits are encapsulated in a 5 mm × 5 mm × 1.3 mm quad-flat no-leads package using the plastic molding technology. The system level characterization of the developed six-DOF inertial sensors have been implemented. Several reliability tests conducted according to the relevant JEDEC standards prove that the packaged sensors are highly reliable and robust for a wide range of operating environments.

Voltage-Dependent Activation Energy Maps for Analytic Lifetime Modeling of NBTI Without Time Extrapolation

To enable MOSFETs lifetime extrapolation of up to 10 years, bias temperature instability (BTI) is commonly accelerated via increased stress voltage and increased temperature. We demonstrate that BTI can be described by a unique activation energy map including the voltage and temperature dependence of stress and recovery and use capture and emission time maps to model the time dynamics responsible for the threshold voltage shift of BTI. Based on this approach, we present a new measurement technique, further called temperature-accelerated measure-stress-measurements (TA-MSM) enabling lifetime modeling of BTI without any time extrapolation. We show the application of this technique to simulate standard qualification measurements, fast wafer-level reliability measurements as well as the degradation after ac and dc burn-in stress. In addition, we show that the TA-MSM technique is a valuable tool for the study of the permanent component and the recently discovered reverse recovery effect.

Concurrent wafer-level measurement of longitudinal and transverse effective piezoelectric coefficients (d33,f and e31,f) by double beam laser interferometry

In a recently published paper [S. Sivaramakrishnan et al., Appl. Phys. Lett. 103, 132904 (2013)], the electrode-size dependence of the longitudinal effective piezoelectric coefficient (d33,f) of piezoelectric thin films measured by double beam laser interferometry was shown to be due to the substrate clamping effects. It was also shown that the true d33,f is measured when the ratio of the electrode size to the substrate thickness is approximately unity, in the case of a substrate with isotropic elastic properties and a Poisson's ratio of ∼0.3. In this paper, we further investigate the dependence of the critical ratio (rc) of the electrode size to the substrate thickness at which the true d33,f is measured on the substrate Poisson's ratio for isotopic substrates and for the important case of the anisotropic Si substrate. It turns out that it is the out-of-plane Poisson's ratio (-s13/s11) that is relevant for this measurement technique and not the in-plane Poisson's ratio which is highly anisotropic for the (001) oriented Si. Furthermore, we show that the transverse effective piezoelectric coefficient (e31,f) can also be determined from the same measurement of the electrode size dependence of d33,f. This provides a convenient non-destructive wafer-level measurement technique for the determination of both the piezoelectric coefficients simultaneously. Moreover, this technique is also capable of measuring e31,f under varying electric field excitation which is important for many applications such as actuators.

High-throughput atomic force microscopes operating in parallel.

Atomic force microscopy (AFM) is an essential nanoinstrument technique for several applications such as cell biology and nanoelectronics metrology and inspection. The need for statistically significant sample sizes means that data collection can be an extremely lengthy process in AFM. The use of a single AFM instrument is known for its very low speed and not being suitable for scanning large areas, resulting in a very-low-throughput measurement. We address this challenge by parallelizing AFM instruments. The parallelization is achieved by miniaturizing the AFM instrument and operating many of them simultaneously. This instrument has the advantages that each miniaturized AFM can be operated independently and that the advances in the field of AFM, both in terms of speed and imaging modalities, can be implemented more easily. Moreover, a parallel AFM instrument also allows one to measure several physical parameters simultaneously; while one instrument measures nano-scale topography, another instrument can measure mechanical, electrical, or thermal properties, making it a lab-on-an-instrument. In this paper, a proof of principle of such a parallel AFM instrument has been demonstrated by analyzing the topography of large samples such as semiconductor wafers. This nanoinstrument provides new research opportunities in the nanometrology of wafers and nanolithography masks by enabling real die-to-die and wafer-level measurements and in cell biology by measuring the nano-scale properties of a large number of cells.

High immunity wafer-level measurement of MHz current

Abstract Wafer-level characterization of functional prototypes of solid state current sensors is usually the first step in the development stage, therefore a dedicated wafer-level measurement systems are required. Especially for MHz characterization, where electromagnetic interference issues became strongly relevant. Thus, for frequencies above 1 MHz, a sophisticated measurement techniques are needed, because parasitic couplings can significantly affect sensor response and other signal processing stages, causing errors or malfunction of the whole system. We propose technique for high immunity MHz current measurement by solid state sensor in wafer-level configuration. The system is especially well-suited for MHz characterization, where electromagnetic interference issues become highly relevant. We showed that balanced transmission provides possibility to reduce interference in the sensor biasing circuit of about 60 dB compared to single-ended method. The effectiveness of the proposed technique was tested in monitoring MHz current in the external line by single magnetoresistive sensors on wafer level.

Wafer level measurements and numerical analysis of self-heating phenomena in nano-scale SOI MOSFETs

We present an experimental technique and a Finite Element thermal simulation for the determination of the temperature elevation in Silicon on Insulator (SOI) MOSFETs due to self-heating. We evaluate the temperature elevation in two steps, as we calibrate the gate resistance over temperature with the transistor at off state at a first stage, and then we deduce the temperature elevation through gate resistance measurements. We simulate the self-heating phenomena in a Finite Elements Method (FEM) environment, both with 2D and 3D models. In order to set up the simulations, we weight the effects of several parameters, such as thermal material properties, the modeling of heat generation and a careful setting of boundary conditions. We present typical temperature fields and local heat fluxes, thus giving concrete indications for solving thermal reliability issues. Simulation results show temperature elevations up to approximately 120K in the hot spot, 70K in the gate and 7K in the Back End of Line (BEoL). The 3D model gives results that are satisfying over the whole set of MOSFETs we consider in this work. Temperature elevation strongly depends on physical dimensions, where transistors endowed with shorter gates suffer from more severe self-heating. We propose a simplified model based on geometrical parameters that predict maximum and gate temperatures, obtaining satisfying results. Since correlation with measurements confirms the correctness of our model, we believe that our simulations could be a useful tool to determine accurate reliability rules and in a context of thermal aware design.

Alternative Highly Homogenous Drift Layer Doping for 650 V SiC Devices

A new method for homogenous drift layer doping is introduced. Instead of in-situ doping during epitaxial growth a subsequent high energy ion implant step is used to dope the drift layer of 650V MPS (Merged-PN-Schottky) diodes. In order to avoid multiple implant steps with various energies for emulating a box-like doping profile, a novel “energy filter” membrane is used to transform the monochromatic ion beam to a beam with a continuous energy spectrum suited for box-like doping. The electrical characteristics of the diodes manufactured by this means show a very homogenous blocking behavior on wafer level, however the expected improved homogeneity in differential resistance of the wafers could not be confirmed by wafer level measurements. More work is needed to understand this discrepancy between experiment and theory.

Waveguide-Based Technique for Wafer-Level Measurement of Phase and Group Effective Refractive Indices

A novel optical technique for multipoint on-wafer testing is reported. The technique exploits an integrated optical waveguide named point reflector optical waveguide (PROW) carrying multiple sensing probes based on lumped reflectors. PROW can be placed on the wafer along the desired paths, is compatible with chips tiling, requires a very small dedicated area and is here exploited to map the on-wafer distribution of the phase and group effective indices with an accuracy down to 10 -3 . The technique is useful to retrieve and map the variations of the physical and geometrical properties of the waveguides (e.g., width and core material composition) on the investigated wafer area. The potential of the PROW is here demonstrated on a InP wafer but can be readily extended to other platforms.

Sol-gel doped-PZT thin films for integrated tunable capacitors

Integrated metal-insulator-metal (MIM) capacitors using sol-gel PZT doped with lanthanum (La, PLZT), manganese (Mn, PMZT) and niobium (Nb, PNZT) were successfully processed and characterized for tunable applications. Dielectric properties of doped-PZT were investigated and compared to those of pure PZT. Wafer-level measurements were conducted with a particular attention on tunability evaluation under DC bias voltage. Tunability, leakage current density and breakdown voltage of pure PZT thin films were 77.6% (i.e. 4.5:1) at 10kHz/10V, 4.8.10−5 A/cm2 at 870kV and 37.5V (i.e. 1.63 MV/cm) respectively. The breakdown voltage increased by 25% with La doping and by 50% with Nb and Mn. The lowest leakage current were achieved by PNZT (7.0.10−7 A/cm2 at 870kV) while PMZT films exhibited an outstanding tunability reaching 88.8% (i.e. 8.9:1) at 100 kHz and 20V. Enhanced performances of the developed doped-PZT were compared to the state of the art. Results indicate that electrical properties of sol-gel doped-PZT achieved those of conventionally deposited materials. It is noteworthy that obtained PMZT tunability is among the highest ones reported in the literature for PZT-derived thin films but also for other piezoelectric materials.

3-D Probe: Low-Cost Variation Modeling Using Intertest-Item Correlations

Process variation models for variation tolerant designs are developed through expensive silicon characterization. This paper presents a low-cost variation characterization method that takes advantage of correlations between test items. The proposed method is based on compressed sensing (CS), a new innovative theory in signal processing and information theory, and we formulate the problem of accounting for the correlations in the form of standard CS problems, allowing us to leverage advances in CS theory. We consider wafer-level measurement results for multiple test items a 3-D signal and propose the sparsifying transform that combines the 2-D discrete cosine transform and the Karhunen-Loéve transform. Our experimental results show that the proposed method reduces the number of samples required for the same accuracy up to 2X compared to virtual probe when two test items are used.