(Invited) Understanding Self-Heating in FinFETS and Its Impact on Metal Interconnect

Abstract

Self-Heating (SE) in FinFETs can be of significant concern for reliability of back-end-of-line (BEOL) interconnects due to electromigration (FM) failure, which is a highly sensitive degradation mechanism at elevated temperatures (1, 2). Temperature levels of ≥5°C due to front-end-of-line (FEOL) self-heating at M1 lines can impact the circuit’s reliable operation (3). The confined heat due to self-heating in FinFETS can flow vertically and laterally to the local interconnects and increasing the metal temperature thereby accelerating the EM failure rate probability. Furthermore, while FinFETs provide the performance, power and scaling advantages over planar devices the local self-heating can potentially affect device performance and exacerbate the effects of various reliability mechanisms (4). It is, therefore, imperative to understand the quantification of self-heating in FinFETs and its reliability implications in the devices, circuits and metal interconnects.In this presentation we will discuss several experimental methodologies to quantify SH using wafer level measurements by implementing three different types of electrical sense elements. The sensing schemes evaluate the surround heat sensing using the electrical characteristic of a neighboring FET device and a local heat sensing element using a 4-terminal kelvin contact to measure the thermal coefficient of resistance of the metal gate. We will evaluate the proximity and effectiveness of these sense elements. We will also investigate the impact of SH on logic circuits using a simple ring-oscillator circuit. The characteristics will be validated through predictive thermal simulations. From the results it is inferred that dense circuit applications such as clock buffers are required to be studied more carefully for its impact of self-heating on upper metal lines. This is particularly critical for technologies such as SOI FinFETs where heat generated by frontend-of-line devices is being forced through the upper metal lines due to the buried oxide where self-heating impact is 5x higher compared to bulk FinFET technology.The author acknowledges the collaborators of Globalfoundries, especially Dr. Peter Paliwoda, for the technical discussion.References W. Chang, S.E. Liu, B.L. Lin, C.C. Chiu, Y.-H. Lee and K. Wu, IEEE IRPS, 2F.6.1, (2015).S-W. Yoo, H. Kim, M. Kang, and H. Shin, of Semicon. Tech and Sc, vol.16(2), 204, (2016).Peter Paliwoda, Doctoral Dissertation, https://digitalcommons.njit.edu/dissertations/1389, NJIT, 1389, pp. 96, (2018).Paliwoda, Z. Chbili, A. Kerber, T. Nigam, K. Nagahiro, S. Cimino, M. Toledano-Luque, L. Pantisano, B.W. Min, and D. Misra, IEEE Trans. on Dev. and Mat. Reliability, vol. 19(2) (2019).