Wafer Foundry Research Articles

A Critical Review of Lithography Methodologies and Impacts of Topography on 2.5-D/3-D Interposers

This paper analyzes the lithography design rules in package foundry and wafer foundry and reviews the major lithography techniques for package redistribution layer (RDL) fabrication for panel level 2.5D/3D interposers, fan-out packages and heterogeneous integration. The techniques surveyed in this paper are- contact aligners, projection aligners/steppers, laser direct writing (LDW) and laser ablation, capable of resolving routing line and space (L/S) of 0.8-1.5 μm with aspect ratio (AR) ≤ 5 and creating microvia with diameter of 1.5-2.0 μm at via pitch ≤5μm. The biggest challenge of advanced packaging is scaling the critical dimensions (CDs) on package to keep up with the pace of scaling of the bump pitch. In addition, there is a critical need for patterning fine lines-and-spaces with high aspect ratio to have low resistance traces. These high AR ultra-fine lines and ultra-fine pitch vias are crucial for meeting the needs of high-bandwidth die-to-die interconnections at high input/output (I/O) densities. All these challenges are mainly driven by lithography. With the development of advanced photoresists (PRs), the resolution factor K1 in projection lithography reduces from 0.66 to 0.39, improving the resolution by 40% without the negative impacts on the depth-of-focus (DOF). This paper also discusses the specific lithography challenges associated with topography of multi-layer RDL as well as their impacts on the fabrication of fine features. The fine pitch microvias can be a solution for scaling the I/O pitch down to 5-10 μm as a bumpless way to connect copper pads of known-good-dies to known-good- substrates in fan-out packages.

Monolithic Reverse Blocking 1.2 kV 4H-SiC Power Transistor: A Novel, Single-Chip, Three-Terminal Device for Current Source Inverter Applications

Current sourceinverters (CSIs) require power switches with first quadrant current conduction and gate-controlled output characteristics as well as reverse blocking capability. Experimental demonstration of a SiC monolithic reverse blocking transistor (MRBT) suitable for CSI applications is described in this letter. The proposed device is based on the integration of a SiC JBS diode with a SiC power <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> on the same chip. The cathode of the SiC JBS diode is connected to the drain of the SiC power <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> by their common N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> substrate. The proposed device structure creates a novel SiC-based unipolar single-chip three-terminal transistor with reverse blocking capability. The measured characteristics of a 1.2 kV 4H-SiC MRBT, fabricated in a commercial six-inch wafer foundry, are reported in this letter. The devices show a diode-like <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -state characteristic with a low knee voltage of 1.3 V and an <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -state voltage drop of 2.8 V at 5 A. The measured reverse transfer capacitance and output capacitance for the MRBT at a drain bias of 2 and 1000 V are a factor of ∼3x and ∼1.6x smaller than the measured values for the internal <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> device. Switching measurements show a 12% reduction in the gate-drain charge for the MRBT compared with the internal <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> which is favorable for reducing switching losses.

Fuzzy tree classification system for fault diagnosis on Ion implanter

Ion implanter is critical to modern integrated-circuit (IC) manufacturing. Ion implanter requires a long process due to low acceleration and high concentration process, which results in low productivity and becomes a bottleneck in the semiconductor fabrication. Furthermore, the wafer is not re-workable if existing error operation either caused by the operator or the machine. Therefore, it is important to develop a real-time fault detection system to minimize the probable down time of the ion implanter. In this work, a real-time fault detection system, which is based on the Fuzzy Tree Classification Systems (FTCS), is proposed to monitor the operation of the Eaton NV6200A/AV ion implanter. Two datasets, the 26-recipe and the 42- recipe cases, provided by a renowned wafer foundry in Taiwan were used to test the performance of the proposed FTCS. The datasets were obtained through the SECS-II interface. Test results demonstrate that the proposed FTCS can work real-time for fault detection of the Eaton NV6200A/AV ion implanter.

Diagnostic-driven yield engineering under atypical wafer foundry conditions

Typically, diagnostic-driven yield engineering consists of two sequential steps- data mining and failure analysis. Data mining seeks early feedback on suspected manufacturing process weakness while failure analysis reveals the physical defect to understand the root cause. However, under atypical conditions such as that in a wafer foundry environment, sufficient information is not available to attain optimal outcomes. Specifically, during volume data analysis, although Root Cause Deconvolution has the ability to predict process weakness using an unsupervised learning algorithm, it only works on random defects. Additionally, GDS layout of IP-secure product might also not be available to a foundry impeding physical failure analysis. Motivated by heightened demands on wafer foundries to deliver faster yield ramp to gain the competitive edge, this paper proposes solutions to overcome these limitations. An enhanced analytical scheme that offers early insights into process weakness (frontend and backend differentiation) regardless of fail mode, and a solution that enables physical failure analysis in the absence of direct access to GDS layout are proposed. An automated approach that captures image snapshots of suspected polygons without compromising confidentiality of the GDS content of IP-protected product is also developed. Experimental results will be presented as an illustration.

Combining an automatic material handling system with lean production to improve outgoing quality assurance in a semiconductor foundry

This research uses a case study methodology to investigate ways of improving the outgoing quality assurance (OQA) processes of a 12-inch wafer foundry. It applies the value stream mapping method of lean production to analyse the wafer OQA processes. The study ensures that all outgoing wafers satisfy customers’ requirements without waste. In this paper, a current state map is used to locate potential waste and problematic process flows. Meanwhile, system simulation is adopted to construct the automatic material handling system and the equipment, transportation, and dispatching automation production module for the OQA processes—namely, the To-Be model and the future state map. The empirical results show that, for the To-Be model, the total lots of three customers per month increased from 3,106 to 3,719 pieces—about a 20% increase—and that the average product cycle time for customers A, B, and C dropped by 43.67%, 57.91%, and 58.39%, respectively. Furthermore, the operators’ utilisation rate increased from 61% of 10 operators on the day and night shifts to 87.26% of seven operators on the day and night shifts—about a 30% decrease of labour costs. Therefore, this study applies lean production (removing the non-value-added activities) and automation to improve the case company’s wafer OQA processes.

Ultrahigh-Q silicon racetrack resonators

An ultrahigh-Q silicon racetrack resonator is proposed and demonstrated with uniform multimode silicon photonic waveguides. It consists of two multimode straight waveguides connected by two multimode waveguide bends (MWBs). In particular, the MWBs are based on modified Euler curves, and a bent directional coupler is used to achieve the selective mode coupling for the fundamental mode and not exciting the higher-order mode in the racetrack. In this way, the fundamental mode is excited and propagates in the multimode racetrack resonator with ultralow loss and low intermode coupling. Meanwhile, it helps achieve a compact 180° bend to make a compact resonator with a maximized free spectral range (FSR). In this paper, for the chosen 1.6 μm wide silicon photonic waveguide, the effective radius R eff of the designed 180° bend is as small as 29 μm. The corresponding FSR is about 0.9 nm when choosing 260 μm long straight waveguides in the racetrack. The present high-Q resonator is realized with a simple standard single-etching process provided by a multiproject wafer foundry. The fabricated device, which has a measured intrinsic Q-factor as high as 2.3 × 10 6 , is the smallest silicon resonator with a &gt; 10 6 Q-factor.

Construct a Wafer Foundry System in Manufacturing Industry Using Heuristic Algorithms

Construct a Wafer Foundry System in Manufacturing Industry Using Heuristic Algorithms

A Stochastic Programming Model to Solve the Capacity Expansion Problem Considering Auxiliary Tools: A Semiconductor Foundry Case

This study developed an extended stochastic programming model for the deterministic approach proposed by Chen, Chen and Liou [1]. Capacity planning, which plays a role in production planning, is a challenging problem for the semiconductor manufacturing industry. This study dealt with the uncertain demands of customers for a foundry industry in Taiwan. Through three scenarios, the stochastic programming model was exploited to solve the optimal medium-term capacity planning problem. The data collected from a real wafer foundry in Taiwan were treated as a fundamental scenario to demonstrate the value of the proposed stochastic programming model. The forecast demand variations in other scenarios complied with a normal distribution. The effect of the different probability distributions of demand scenarios on capacity allocation was considered. Changes in the customer order fulfillment rate or capacity utilization rate were analyzed from a series of capacity planning tests with varying demands of the initial customer. Based on different demand scenarios, the numerical results in this study revealed the concordance between the deterministic model and the proposed stochastic programming model. This stochastic programming model also expressed the flexible consideration of auxiliary tools and the increasing number of certified fabrication to the capacity planning problem in the wafer foundry.

Big data analytics for forecasting cycle time in semiconductor wafer fabrication system

In order to improve the prompt delivery reliability of the semiconductor wafer fabrication system, a big data analytics (BDA) is designed to predict wafer lots’ cycle time (CT), which is composed by four parts: data acquisition, data pre-processing, data analysing and data prediction. Firstly, the candidate feature set is constructed to collecting all features by analysing the material flow of wafer foundry. Subsequently, a data pre-processing technique is designed to extract, transform and load data from wafer lot transactions data-set. In addition, a conditional mutual information-based feature selection process is proposed to select key feature subset to reduce the dimension of data-set through data analysing without pre-knowledge. To handle the large volumes of data, a concurrent forecasting model is designed to predict the CT of wafer lots in parallel as well. According to the numerical analysis, the predict accuracy of the presented BDA improves clearly with the increase in data size. And, in the large-scale data-set, the BDA has higher accuracy than linear regression and back-propagation network in CT forecasting.

New fuzzy method for improving the precision of productivity predictions for a factory

Predicting productivity is crucial in managing a factory. However, optimizing the precision of productivity prediction is not easy because two concerns must be addressed simultaneously: the hit rate and the average range. To enhance the precision of predictions of the productivity of a factory, a new fuzzy method is proposed in this paper. First, the hit rate and average range are merged into the cost for inclusion (CFI) to evaluate the precision of productivity prediction more reasonably. Subsequently, the CFIs of a traditional probabilistic method and four existing fuzzy methods are compared. According to the results of the comparison, the 100 (1 – α) % inclusion interval is used to reduce the CFI at the expense of a slight decrease in the hit rate. Subsequently, to improve the hit rate and CFI for testing and unlearned data, a selectively widened inclusion interval is adopted. Some theoretical properties of the proposed methodology are proven. In addition, data from two real cases, a dynamic random access memory (DRAM) factory and a wafer foundry, were used to illustrate the applicability of the proposed methodology. According to the experimental results, the wafer foundry exhibited a higher maturity level of productivity learning than the DRAM factory. In addition, the proposed methodology outperformed the existing probabilistic and fuzzy methods in minimizing the CFI (i.e., maximizing the precision). Further, the selectively widened inclusion interval was proven to be an effective means for trading the training performance for the testing performance.

Probing weak localization in chemical vapor deposition graphene wide constriction using scanning gate microscopy

Low-temperature scanning gate microscopy (LT-SGM) studies of graphene allow one to obtain important spatial information regarding coherent transport such as weak localization (WL) and universal conductance fluctuations. Although fascinating LT-SGM results on pristine graphene prepared by mechanical exfoliation have been reported in the literature, there appears to be a dearth of LT-SGM results on chemical vapor deposition (CVD)-grown graphene whose large scale and flexible substrate transferability make it an ideal candidate for coherent electronic applications. To this end, we have performed LT-SGM studies on CVD-grown graphene wide constriction (0.8 μm), which can be readily prepared by cost-effective optical lithography fully compatible with those in wafer foundry, in the WL regime. We find that the movable local gate can sensitively modulate the total conductance of the CVD graphene constriction possibly due to the intrinsic grain boundaries and merged domains, a great advantage for applications in coherent electronics. Moreover, such a conductance modulation by LT-SGM provides an additional, approximately magnetic-field-independent probe for studying coherent transport such as WL in graphene and spatial conductance variation.

Mixed-mode cohesive zone parameters for sub-micron scale stacked layers to predict microelectronic device reliability

With continued feature size reduction in microelectronics and with more than a billion transistors on a single integrated circuit (IC), on-chip interconnection has become a challenge in terms of processing-, electrical-, thermal-, and mechanical perspective. Today’s high-performance ICs have on-chip back-end-of-line (BEOL) layers that consist of copper traces and vias interspersed with low-k dielectric materials. These layers have thicknesses in the range of 100nm near the transistors and 1000nm away from the transistors and near the solder bumps. In such BEOL stacks, cracking and/or delamination is a common failure mode due to the low mechanical and adhesive strength of the dielectric materials as well as due to high thermally-induced stresses. However, there are no available cohesive zone models and parameters to study such interfacial cracks in sub-micron thick microelectronic layers.This work focuses on developing framework based on cohesive zone modeling approach to study interfacial delamination in sub-micron thick layers. Such a framework is then successfully applied to predict microelectronic device reliability. As intentionally creating pre-fabricated cracks in such interfaces is difficult, this work examines a combination of four-point bend and double-cantilever beam tests to create initial cracks and to develop cohesive zone parameters over a range of mode mixity. Similarly, a combination of four-point bend and end-notch flexure tests is used to cover additional range of mode mixity. In these tests, silicon wafers obtained from wafer foundry are used for experimental characterization. The developed parameters are then used in actual microelectronic device to predict the onset and propagation of crack, and the results from such predictions are successfully validated with experimental data.

Enhancement of Inventory Management for the Wafer Manufacturing Industry by Combining Market Demand Forecast and Demand-Pull Replenishment

Abstract Theory of constraints (TOC) uses a demand-pull replenishment strategy with buffer management (DPBM) to effectively manage inventory. This strategy has been demonstrated to perform better than traditional inventory strategies, such as (s, S), (s, Q), (R, S), (R, s, S) policies. However, the replenishment lead time is long, and demand changes rapidly in the semiconductor industry. These characteristics cause problems in managing semiconductor inventory and complicate the inventory replenishment strategy. In order to effectively solve the issue of inventory management, this paper proposes a novel approach to improve the classical DPBM by using market demand forecast information and demand-pull replenishment to effectively manage inventory in the semiconductor industry. In numerical verification, this paper used real data provided by a wafer foundry in Taiwan to demonstrate the feasibility and effectiveness of the proposed approach. Simulated scenarios that account for different patterns of demand and different degrees of accuracy of the demand forecasts were generated to test the performance of the proposed approach. After comparing the result that was obtained from the proposed approach with the one from the classical DPBM, it was found that the proposed approach can reduce the average inventory and does not adverse the level of service as long as the demand forecasts are not too far from the real demand.

CoC (Chip on Chip) or FtoF (Face to Face) - PossumTM Technology for 3D MEMS and ASIC eliminating the need of TSV or Wire Bonding

This paper describes the ongoing 3 years research and development at Amkor Technology on CoC (Chip on Chip)/FtF (Face to Face) – PossumTM technology. This technology has showed a lot of interests from the microelectronics customers/industries because of its various advantages, which include a) providing smaller form factor (SFF) to the final package, b) more functionalities (dies) can be incorporated/assembled in one package, c) improving the electrical performance - including lower parasitic resistance, lower power, and higher frequency bandwidth, and d) Opportunity for lower cost 3D system integration. Unlike other 3D Packaging technology (e.g. using TSV (Through Silicon Vias)) that requires some works in the front stream (wafer foundry) level, needs new capitals for machines/equipments, and needs modified assembly lines; CoC/FtF technology uses the existing flip Chip Attach (C/A) or TC (Thermal Compression) equipment/machine to perform the assembly joint between the two dies, which are named as the mother (larger) die and the daughter (smaller) die. Furthermore, the cost to assemble CoC/FtF is relatively inexpensive while the applications are very wide and endless, which include the 3D integration of MEMS and ASIC. The current MEMS packaging and test cost contributes about 35 to 45% to the overall MEMS unit cost. WLC (Wafer Level Capping) with wire bonding have been widely used for mass production for accelerometer (e.g. ADI and Motorola), gyroscope (e.g. Bosch and Invensense), and oscillator /timer (e.g. Discera). The WLC produce drawbacks of a large form factor and the increase in the capacitive and electrical resistances. Currently, the industries have been developing a new approach of 3D WLP (Wafer Level Packaging) by using a) TSV MEMS cap with wire bonding (e.g. Discera), b) TSV MAME cap with solder bump (e.g. Samsung, IMEC, and VTI), and c) TSV MEMS wafer/die with cap (e.g. Silex Microsystems). The needs of TSVs in the 3D WLP will add the packaging cost and reduce the design flexibility is pre-TSV wafer is used. “Amkor CoC/FtoF – PossumTM” is an alternative technology for 3D integration of MEMS and ASIC. CoC/FtoF – PossumTM does not require TSV or wire bonding; Miniaturizing form factor of 1.5 mm x 1.5 mm x 0.95 mm (including the package) of MEMS and ASIC can be achieved by using CoC/FtoF – PossumTM while Discera's design of 3D WLP requires substrate size &amp;gt; 2 mm x 2 mm. CoC/FtoF – PossumTM will likely produce packaging cost which is lower than WLC or 3D WLP – TSV at the same time the customer is benefited from smaller FF and reduced electrical/parasitic resistance. CoC/FtoF – PossumTM can be applied to any substrates including FCBGA and laminate. This technology also can be applied to package multiple MEMS microsensors, together with ASIC, microcontroller, and wireless RF to realize the 3D system integration.

Application of SEM API on PWQ Wafer SEM Review

Process Window Qualification (PWQ) is a good and well-established method to find systematic defects with high sensitivity and to qualify new masks and OPC revisions. The PWQ methodology is utilized to provide an extensive defectivity characterization to determine the absolute best conditions for focus and dose. This is achieved by taking into account the defectivity in the whole die and capturing all potential systematic defects. [1] This in turn had driven to more and more SEM review on this kind of PWQ wafer in wafer foundry. Manual SEM review of this PWQ wafer is time consuming and spending a lot of man power. In this paper, a new method of reviewing the PWQ wafer with API method and how it helps to resolve the current manual SEM review limitations is introduced.

Pure Play

The paper presents pure play wafer foundry in Taiwan to establish a dedicated foundry semiconductor industry. The dedicated foundry industry has become an integral and symbiotic part of the overall semiconductor industry. It now produces approximately 33% of the world's logic ICs (by value of products manufactured), and it has greatly quickened the pace of innovation in logic ICs. There are now hundreds of IC companies competing with each other, rather than dozens as in the 1980s, and competition quickens innovation. None of the fabless com panies has to carry the heavy capital weight of a fab or the large R&D expense of process development. They can therefore concentrate on system architecture and design. Fur thermore, this increase in the num ber of successful IC companies hasallowed the creation of a significant amount of shareholder wealth. The impact of a dedicated foundry on the IC industry is still growing. While TSMC's customers have become more competitive, it is TSMC's mission to be the trusted provider of technology and capacity to the global logic IC industry. All this occurred in just over 20 years and germinated from an idea that very few people paid attention to. Fewer still thought that it would succeed.

SMIC Welcomes an Old-Timer Back to Take Up the Reins [Associate Editor's View

Semiconductor Manufacturing International Corporation (SMIC, NYSE: SMI, SEHK: 981), the largest and most advanced semiconductor wafer foundry in mainland China, announced on Friday, 5 August 2011, the appointment of Tzu-Yin Chiu as CEO and executive director of the board, ending the series of unfortunate events affecting the company's future for more than a month since the death of its nonexecutive board chair, Shangzhou Jiang, on 27 June.

The design of key performance indicators on technology development of a wafer foundry

Due to capital intensive characteristics, R&D departments always share production equipment with manufacturing departments in the wafer foundry industry. The goal of key performance indicators (KPIs) among these two departments is contradictory, a situation that results in longer R&D cycle times and delays in time-to-market. To solve the problem, this study has adapted the concepts of X-factor theory to construct an R&D engineering lot management model. There are two KPIs adapted in this model. The first KPI, the X-factor, is applied to trace on-time delivery performance of the new R&D technology. The second KPI, F-factor, is regarded as an index that reflects the holding cost and manufacturability of R&D lots, and simultaneously evaluates the maturity of the technology. Furthermore, a set of real data from the Fab is applied to examine the effectiveness of this model. The results reveal that this model successfully improves operational performance and shortens the R&D cycle time, which ultimately enables a factory to achieve a global optimization.

Combined DEMATEL technique with a novel MCDM model for exploring portfolio selection based on CAPM

This research proposes a novel MCDM model, including DEMATEL, ANP, and VIKOR for exploring portfolio selection based on CAPM. We probe into the influential factors and relative weights of risk-free rate, expected market return, and beta of the security. The purpose of this research is to establish an investment decision model and provides investors with a reference of portfolio selection most suitable for investing effects to achieve the greatest returns. Taking full consideration of the interrelation effects among criteria/variables of the decision model, this paper examined leading semiconductor companies spanning the hottest sectors of integrated circuit (IC) design, wafer foundry, and IC packaging by experts. Empirical findings revealed that risk-free rate was affected by budget deficit, discount rate, and exchange rate; expected market return was affected by country risk, industrial structure, and macroeconomic factors; and beta of the security was affected by firm-specific risk and financial risk. Also, the factors of the CAPM possessed a self-effect relationship according to the DEMATEL technique. In the eight evaluation criteria, macroeconomic criterion was the most important factor affecting investment decisions, followed by exchange rate and firm-specific risk. In portfolio selection, leading companies in the wafer foundry industry outperformed those in IC design and IC packaging, becoming the optimal portfolio of investors during the time that this study was conducted.

A Systematic Methodology For Low Yield Excursion Analysis

Due to the complicated process and huge cost of a modern semiconductor wafer foundry, maintaining stable yield is very critical. If the yield killer is not identified, no containment actions can be taken; if there are no containment actions, the impact will continue and the yield loss will enlarge. In this paper, we have proposed a new systematic methodology for low yield excursion analysis. It integrated Kepner-Tregoe (KT) method and fishbone factor analysis to identify the real yield killer in an efficient and effective manner. From the real case application, it was proven that KT method and fishbone factor analysis can be integrated and resolved the issue successfully. This methodology has great potential to extend to other complicated and urgent daily management issues in a semiconductor fabrication plant.