Wafer Fabrication Research Articles

Multiobjective Scheduling of Dual-Blade Robotic Cells in Wafer Fabrication

As a kind of robotic cells, cluster tools are widely used for semiconductor wafer fabrication processes since they provide a reconfigurable and efficient environment. With recent advances in new semiconductor materials, the circuit line width has continuously being shrunk down, which brings new challenges for manufacturers. They require that a wafer should be moved away from a processing chamber as soon as possible after its processing is finished. To ensure high-quality integrated circuits in a wafer, its post-processing residency time must be minimized. It is also highly desirable to maximize the throughput of robotic cluster tools. This article aims at scheduling such tools with multiple objectives subject to wafer residency time constraints. To do so, new algorithms are proposed to calculate robot waiting time delicately upon the analysis of particular events of robot waiting for dual-blade robotic tools and optimally schedule such tools. The numerical results of industrial examples show that the proposed algorithms can provide an effective method to find schedules for dual-blade cluster tools such that multiple objectives are optimized.

Performance evaluation of deterministic flow lines considering multiclass customer and random setups

Inspired by flexible manufacturing systems with setups, in this study, we investigate the steady-state behavior of flow line models with deterministic service durations. In such systems, different types of products with different batch sizes are produced in a single production line, and a setup is required when switching from one type of product to another. In this study, we aim at analyzing the effect of different setups on a system’s performance metrics, i.e., the maximum production rate and delay distribution of a product experienced inside the system. The maximum production rate of a deterministic flow line is the reciprocal of its bottleneck process time; however, the different setups existing in a system complicate the analysis. Furthermore, setups are necessary in flexible manufacturing systems. The systems that are the subject of our model are steel pipe manufacturing process and semiconductor wafer fabrications. Additionally, we obtain and analyze a two-dimensional, discrete-time, time-homogeneous Markov chain model to derive the system’s performance measures.

Qualification Management in Wafer Fabs: Optimization Approach and Simulation-Based Performance Assessment

Machines need to be individually qualified to run lots of certain families in semiconductor wafer fabrication facilities (wafer fabs). A qualification time window that lasts a couple of days is associated with each family and each tool. The time window can be reinitialized with additional qualification effort as needed and can be extended by on-time processing of qualified families. A mixed-integer linear programming formulation is proposed. The objective function takes into account the backlog costs and inventory holding costs. Moreover, it penalizes qualifications. The optimization approach is applied in a rolling horizon setting using a wafer fab simulation model. The demand for a planning window of several periods is derived using feedback from the shop floor. The results of the simulation experiments demonstrate that an appropriate tradeoff between production objectives and performed qualifications can be achieved by an appropriate configuration of the model. Note to Practitioners —In this article, we propose a mathematical programming-based approach to decide when the tools in wafer fabs have to be qualified for a certain family. These decisions have high practical relevance because qualifications are expensive and time-consuming. A dispatching scheme to implement the qualification decisions is designed. The overall approach is assessed in a rolling horizon setting using a simulation model of a large-scale wafer fab. An appropriate tradeoff between production and qualification goals can be achieved using the proposed approach.

Adaptive Scheduling of Cluster Tools With Wafer Delay Constraints and Process Time Variation

A cluster tool consists of several single-wafer processing chambers and a wafer-handling robot. Cluster tools are widely used for wafer fabrication in semiconductor manufacturing fabs. As the circuit width shrinks down to below 20 or even several nanometers, wafer waiting within a chamber after processing becomes more critical to wafer quality due to residual gases and heat. Conventional tool scheduling rules, such as the swap sequence and the backward sequence, may not satisfy strict upper limits on wafer delays, especially when process times fluctuate randomly. We examine a scheduling problem for cluster tools with strict upper limits on wafer delays under process time variation. We propose a new class of schedules, which not only keeps timing patterns steady as possible but also adapts timing of tasks in response to process time variation so as to satisfy wafer delay constraints robustly. We also derive conditions for which there exists such a schedule. We develop a mixed-integer programming model to find an optimal schedule among such adaptive schedules. By numerical experiments, we show that the proposed scheduling method can effectively cope with tight wafer delay constraints even under large process time variations. Note to Practitioners —As the circuit widths shrink down, residual gases and particles within chambers after processing wafers become more critical to wafer quality. In fact, leading fabs are now cleaning a chamber for each new wafer in order to reduce such quality risk. We propose a new practical method for scheduling tools that can significantly reduce such quality risk caused by wafer waiting within chambers after processing.

Graphene field-effect transistor simulation with TCAD on top-gate dielectric influences

This paper presents the influence of top-gate dielectric material for graphene field-effect transistor (GFET) using TCAD simulation. Apart from silicon-based dielectric that is typically used for top-gate structure, other high-dielectric constant (high-k) dielectric materials namely aluminum oxide and hafnium oxide are also involved in the analysis deliberately to improve the electrical properties of the GFET. The unique GFET current-voltage characteristics against several top-gate dielectric thicknesses are also investigated to guide the wafer fabrication engineers during the process optimization stage. The improvement to critical electrical parameters of GFET in terms of higher saturation drain current and greater on/off current ratio shows that the use of high-k dielectric material with very thin oxide layer is absolutely necessary.

AdaBalGAN: An Improved Generative Adversarial Network With Imbalanced Learning for Wafer Defective Pattern Recognition

Identification of the defective patterns of the wafer maps can provide insights for the quality control in the semiconductor wafer fabrication systems (SWFSs). In real SWFSs, the collected wafer maps are usually imbalanced from the defective types, which will result in misidentification. In this paper, a novel deep learning model called adaptive balancing generative adversarial network (AdaBalGAN) is proposed for the defective pattern recognition (DPR) of wafer maps with imbalanced data. In addition, a categorical generative adversarial network is improved to generate simulated wafer maps in high fidelity and classify the patterns with high accuracy for all defective categories. Taking consideration of the various learning abilities of the DPR model for different patterns into account, an adaptive generative controller is designed to balance the number of samples of each defective type according to the classification accuracy. The experiment results indicated that the proposed AdaBalGAN model outperforms conventional models with higher accuracy and stability for the DPR of wafer maps. Further results of comparative experiments revealed that the proposed adaptive generative mechanism can enhance and balance the recognition accuracy for all categories in the DPR of wafer maps.

A data-driven approach to selection of critical process steps in the semiconductor manufacturing process considering missing and imbalanced data

Semiconductor wafers are fabricated through sequential process steps. Some process steps have a strong relationship with wafer yield, and these are called critical process steps. Because wafer yield is a key performance index in wafer fabrication, the critical process steps should be carefully selected and managed. This paper proposes a systematic and data-driven approach for identifying the critical process steps. The proposed method considers troublesome properties of the data from the process steps such as imbalanced data, missing values, and random sampling. As a case study, we analyzed hypothetical operational data and confirmed that the proposed method works well.

Throughput Estimation Model of Cluster Tool in Semiconductor Manufacturing

Semiconductor manufacturing management system was developed and grown up over the past decades. In order to increase the product yield and enhance the production productivity, cluster tools became the main stream in modern wafer fabrication factories which occupies over 50% of production equipment. Generally, cluster tools are integrated by several components including robots, vacuum chambers (Load locks) and single-wafer process chambers in a module and can be treated as a small factory. The throughput estimation before recipe release is very difficult. However, it is necessary and important for the planning activity. In this work, a throughput estimation model for cluster tools is proposed. The Multiple Regression Analysis is applied to develop a set of throughput estimation equations. A simulation model of cluster equipment including 3 single-wafer process chambers are built to get the historical throughput data for the regression analysis. From the Multiple Regression Analysis, it reveals that different numbers of recipes processed in the same time have to develop different regression model. The major factors in the regression model include numbers of load ports and process time of each recipe. Furthermore, a set of recipes are used to test the accuracy of estimation. Based on the testing results, they revealed that the MAPE is under 3% and the estimation model is accepted in practice to forecast the throughput of recipes for the planning activities.

Computer guided maxillary positioning using osteotomy/plates locating surgical guides in management of maxillary deficiency

Maxillary segment repositioning is essential for esthetic and functional outcomes. Increased success and experience achieved with computer guided Le Fort I osteotomy turned the attention to develop surgical techniques to cope with deficient maxilla solving the problem of the time-consuming manual steps of intermediate wafer fabrication in addition to its inability to adjust the correct vertical position of the maxilla in relation to the skull base. This study aimed to evaluate CAD/CAM generated osteotomy/ plates locating surgical guides in three-dimensional maxillary segment repositioning. Ten patients with maxillary hypoplasia were subjected to virtual model surgery forming corrected 3D skull models for titanium plates pre-bending. Screw holes were marked to the corrected 3D skull models for construction of osteotomy / plates locating surgical guides. Pre-bent plates were installed intra-operatively into the predetermined screw holes. Placement of the plates adjust the depressed maxilla three dimensionally. All patients were clinically and radiographically evaluated pre and post-operatively. Degree of three-dimensional corrective movement were measured and statistically evaluated. CAD/CAM generated osteotomy plates locating surgical guides were proved to be more reliable for three-dimensional maxillary segment repositioning.

HUMAN ERROR REDUCTION PROGRAM THROUGH CANONICAL ACTION RESEARCH (CAR) IN WAFER FABRICATION MANUFACTURING FACILITY

In a wafer fabrication manufacturing facility, thousands of wafers are being processed daily. To manufacture the product, the wafers need to go thru hundreds of steps according to the technologies required. The cycle time to complete a standard product ranges from few weeks to few months, depends on the complexity of the technologies. Due to the difficulty and the complexity of the product, Computer Integrated Manufacturing system (CIM), is widely used as a manufacturing platform. As such, all the processes, equipment and wafers are fully integrated. Nevertheless, not all processes could be processed automatically. In the situation of the halfway processes wafer due to equipment or facility interruption, the wafer, need to be processed manually. Engineers or technicians will manually process the affected wafer according to the specification. The problem arises when; there is a human involvement that ends up with wafers misprocess. The potential revenue lost due to wafer misprocess is vast. Hence, this paper aims to discuss issues related to human error in manufacturing, specifically in Wafer Fabrication Manufacturing Facility. The paper presents partial input for the Canonical Action Research (CAR) that presently being exercised in order to minimize human error by developing a Small Group Activities (SGA) in the manufacturing facility.

Standard wafer with programed defects to evaluate the pattern inspection tools for 300-mm wafer fabrication for 7-nm node and beyond

Background: Standard patterned sample with programed defects (PDs) is effective to evaluate the tool performance of pattern inspection system, but the fabrication of such standard sample, having large area dense patterns with PDs suitable for the evaluation of sub-7-nm node, is difficult. Aim: The goal of this study is to fabricate a standard sample to evaluate the performance of inspection tool for below 7-nm nodes. Approach: We use electron beam lithography with an acceleration voltage of 130 keV to fabricate standard sample. Results: We form large area dense sub-16-nm half pitch (hp) line and space (LS) patterns with PDs on 300-mm-Si-wafers, and 10- to 7-nm hp LS patterns on a 100-mm-Si wafer. Approximately 5-nm PDs with shapes including protrusions, intrusions, bridges, and openings are formed without additional defects. Moreover, pattern-etched Si wafers with 16- to 12-nm hp LS are successfully fabricated. A 100-mm-wafer with patterns is mounted into a 300-mm-Si wafer. Conclusions: The acceleration voltage of 130 keV is sufficient for the fabrication of large area dense pattern with PDs suitable for the evaluation of sub-7-nm node. Moreover, the fabricated standard wafers are useful to evaluate the tool performance of the inspection system for 300-mm wafer fabrication.

General Process Change Qualification framework for Wafer Fabrication

Wafer fabrication is the most value-added processes of semiconductor and electronics industries. The involved processes are state-of-the-art, most expensive, most complicated and highly sensitive. Any process changes require qualification dictated by different industry standards and also internal production performance specifications. The way a semiconductor industry performs qualification is often little known outside the industry and in contemporary literature. The paper offers insights into qualification process for wafer fabrication. Literature is reviewed on qualification in terms of reasons, stages and considerations. A general qualification framework currently employed in a foundry is shared as a valuable example.

CLASSIFICATION AND PREDICTION OF WAFER PROBE YIELD IN DRAM MANUFACTURING USING MAHALANOBIS-TAGUCHI SYSTEM AND NEURAL NETWORK

Wafer yield is a key indicator to pursuing excellence in semiconductor manufacturing. With the increased wafer size, the enhanced complexity and precision of wafer fabrication is possible. Using monitoring to improve the process by predicting the yield has become an important quality issue. Most research uses the number of wafer defects, the area of the wafer, and fixed statistical distribution to predict the yield. Such methods fail to establish a high yield model due to the random and system-wide distribution of wafer defects. This study proposes the Mahalanobis-Taguchi system (MTS) to determine the key variables from the wafer acceptance test (WAT), and establish a classification model of yield grade. The general regression neural network (GRNN) was used to build a predicted model of the wafer probe yield from selected common variables. A real case from a Taiwan manufacturer of dynamic random-access memory (DRAM) is used as an example. It can get the 82 key and significant sequence variables of the WAT, with classification precision of over 90% and the R 2 of the GRNN prediction model at 0.73. Through demonstration, the result can effectively increase the yield and reduce the quality cost in DRAM manufacturing.

A method for wafer assignment in semiconductor wafer fabrication considering both quality and productivity perspectives

In the semiconductor wafer fabrication process, wafers go through a series of sequential process steps. Typically, each process step has several machines, and the wafers are assigned to one whenever they enter the process step. When assigning wafers to machines, it is important to consider both the quality and productivity perspectives. Major semiconductor companies in Korea have recently implemented a wafer assignment system to improve wafer yield, a critical measure for semiconductor quality. This system, however, does not consider the productivity perspective. This paper presents a systematic method for assigning wafers to maximize the wafer yield while satisfying a predetermined target level of productivity. A simple hypothetical example is presented to illustrate the method.

Sampling-based release control of multiple lots in time constraint tunnels

Semiconductor wafer fabrication probably includes the most complex and constrained manufacturing processes due to its intricate and time-varying environment. This paper focuses on time constraint tunnels (TCTs), which can have a very high impact on the yield and reliability of final products. More precisely, the original problem faced by managers of controlling the release of multiple lots in a TCT is addressed in the context of a wafer facility operating in a High-Mix Medium-Volume manufacturing environment. To support the management of TCTs in an industrially acceptable context, a scheduling-based sampling method is proposed to estimate the probability that multiple lots released at the entrance of a given TCT leave this TCT on time. In order to investigate the industrial viability and identify the limitations of the probability-estimation approach, numerical experiments are conducted on real-life data and analyzed through the prism of several relevant performance criteria. Insights gathered from this numerical analysis are then used to discuss the specific management requirements that stem from the criticality of TCTs in semiconductor manufacturing facilities.

Reuse of ScAlMgO4 substrates utilized for halide vapor phase epitaxy of GaN

ScAlMgO4 (SCAM) substrates with a small lattice-mismatch to GaN and c-plane cleavability are promising for fabricating high-quality free-standing GaN wafers. To reduce the cost in the fabrication of free-standing GaN wafers, the reuse of a SCAM substrate is demonstrated. By cleaving a SCAM substrate which has been already utilized for the growth of a thick GaN film by halide vapor phase epitaxy, the atomically flat surface can be obtained. The threading dislocation density of a 320 μm thick GaN film grown on this cleaved SCAM substrate is 2.4 × 107 cm−2, which is almost the same as that on a new SCAM substrate. This result indicates that a SCAM substrate can be reused for GaN growth.

Controllable fabrication and mechanism study of textured ultra-thin silicon wafers via one-step Cu-assisted chemical etching

In this paper, the one-step Cu-assisted chemical etching method is reported for controllable thinning and texturization on mono-crystalline silicon in Cu2+/HF/H2O2 mixture solution. HF and Cu2+ exhibited a synergetic effect on accelerating etching process while H2O2 slowed down the preferential Si (100) etching by oxidizing the Cu atoms. Within optimal 0.15 M Cu2+/4 M HF/0.88 M H2O2 solution, quasi-inverted pyramid-like structures of 2–4 μm in size and a reflectance of 8.46% were obtained at 20 °C. By adjusting the temperature and etching time, ultra-thin silicon wafers with thickness of 19–120 μm were fabricated. Comparing the microstructures obtained at 20 °C and 60 °C, widths and inclination angles were distinct. By illustrating the transportation and distribution of holes during the etching process, the intrinsic connection between thinning and texturization was studied. The etching results, including etching rates and morphologies, were determined by the distribution of holes between the B’ and B” orbitals. In summary, controllable fabrication of textured ultra-thin silicon wafers with desired thickness and microstructures could be achieved by one-step, short-time and low-temperature Cu-assisted chemical etching method, exhibiting a great potential use in ultra-thin silicon solar cells.

Marker Layout for Optimizing the Overlay Alignment in a Photolithography Process

In the photolithography process of wafer fabrication, a mask pattern is transferred to a wafer in a layer-by-layer fashion, and the pattern alignment of adjacent layers is critical to the wafer yield. To enhance the alignment precision, an overlay metrology system measures the overlay error at some markers on the wafer, and the error information is used for constructing an overlay correction model. During the overlay alignment, the layout of the markers has a significant impact on the correction of the overlay error. After the maximum number of available markers has been determined based on the quality and turn-around time of the target device, the positions of those markers should be determined in such a way that the overlay error correction model shows robust performance for future wafers. In this paper, we propose a sparse particle swarm optimization algorithm to find an optimal marker layout in terms of robust performance characterized by the overlay error prediction and irregularity of marker positions. In the experiment, the performance of the marker layouts suggested by several search algorithms was tested on three different layers, and the proposed algorithm demonstrated superiority over the other algorithms.

Recovery of gallium from wafer fabrication industry wastewaters by Desferrioxamine B and E using reversed-phase chromatography approach

Gallium (Ga) is a critical element in developing renewable energy generation and energy efficient systems. The supply of Ga is at risk and needed recycling technologies for its availability in future. This study demonstrated the recovery of Ga3+ from low gallium concentrated wafer fabrication industry wastewaters using the siderophores desferrioxamine B (DFOB) and desferrioxamine E (DFOE). The complexation of Ga3+ by DFOB and DFOE was through hydroxamate group as demonstrated by infrared spectroscopy, nuclear magnetic resonance and density functional theory calculations. The high selectivity of DFOB/E towards Ga3+ was observed due to the formation of highly stable complex. Indeed, due to the formation of such high stability complex, the DFOB and DFOE were able to successfully complex 100% Ga in the two different process water from wafer fabrication industry. For the recovery of the siderophores, a high rate of decomplexation of Ga (>90%) was achieved upon addition of 6 times excess of ethylenediaminetetraacetic acid (EDTA) at pH of 3.5. More than 95% of Ga-DFOB and Ga-DFOE complex were recovered with purity (% of Ga moles in comparison to total moles of metals) of 69.8 and 92.9%, respectively by application of a C18 reversed-phase chromatography column. This study, for the first time, demonstrated a technical solution to the recovery of Ga3+ from the low concentrated wastewater based on siderophores and reversed-phase chromatography. A German patent application had been filed for this technology.

Study on Warpage and Reliability of Fan-Out Interposer Technology

The fan-out interposer (FOI) technology with fine pitch is demonstrated and presented for heterogeneous integration as a cost-effective and enabling technology. The co-design modeling methodology is established for the FOI technology, including wafer process-induced warpage, package assembly warpage, and board-level solder joint reliability to optimize the structure design, wafer process, assembly process, and material selection. Through the wafer warpage modeling, desirable glass carrier, photodielectric, and molding compound materials and interposer structure are suggested to reduce the wafer warpage. Effect of stiffener on assembly induced package warpage is simulated and studied. Board-level solder joint reliability is investigated and optimized based on the simulation results. The optimized materials and the structure design are determined based on the co-design modeling and simulation results to achieve the successful FOI wafer fabrication, assembly process, and board-level reliability for extreme large package with FOI.