Wafer Fabrication Research Articles

Models of Clustered Photolithography Tools for Fab-Level Simulation: From Affine to Flow Line

Fab-level discrete-event simulation is an important practical tool for the analysis and optimization of semiconductor wafer fabricators. In such facilities, a clustered photolithography tool (CPT) is by far the most expensive tool and often the capacity bottleneck. In this paper, we consider linear, affine, flow line, and detailed models of CPTs for use in fab-level simulation. We develop extensions to affine and flow line models and demonstrate exactly how to convert raw CPT data into the various models. Using a detailed CPT model based on industry data as the baseline, numerical experiments are conducted to test the models’ fidelity for cycle time, lot residency time, and throughput. We also compare the computational burden of each model class. Further simulations are conducted to test the models’ robustness to changing fab conditions, e.g., when lot size or train size changes. Flow line models are shown to be more accurate and robust than linear or affine models and require approximately 200 times less computation than detailed models.

Optimal One-Wafer Cyclic Scheduling of Time-Constrained Hybrid Multicluster Tools via Petri Nets

Scheduling a multicluster tool with wafer residency time constraints is highly challenging yet important in ensuring high productivity of wafer fabrication. This paper presents a method to find an optimal one-wafer cyclic schedule for it. A Petri net is developed to model the dynamic behavior of the tool. By this model, a schedule of the system is analytically expressed as a function of robots’ waiting time. Based on this model, this paper presents the necessary and sufficient conditions under which a feasible one-wafer cyclic schedule exists. Then, it gives efficient algorithms to find such a schedule that is optimal. These algorithms require determining the robots’ waiting time via simple calculation and thus are efficient. Examples are given to show the application and effectiveness of the proposed method.

Minimizing total earliness and tardiness on re-entrant batch processing machine with time windows

ABSTRACTThe time window (TW) generalizes the concept of due date. The semiconductor wafer fabrication system is currently one of the most complex production processes, which has typical re-entrant batch processing machine (RBPM). RBPM is a bottleneck. This paper addresses a scheduling of RBPM with job-dependent TWs. According to a general modelling, an improved and new job-family-oriented modelling of the decomposition method that is based on the slack mixed integer linear programming is proposed. First, the complicated scheduling problem of RBPM is divided into sub-problems, which are executed circularly. Then, each one consists of updating, sequencing and dispatching. The objective is to minimize the total earliness and tardiness for job-dependent TWs. In order to evaluate the proposed modelling, the experiments are implemented on the real-time scheduling simulation platform and optimization toolkit ILOG CPLEX. The results show that the improved modelling obtains better solutions in less computation time.

RETRACTED: The Optimal Decision Combination in Semiconductor Manufacturing

Wafer fabrication is a capital-intensive and highly complex manufacturing process. In a wafer fabrication facility (fab), wafers are grouped as a lot to go through repeated sequences of operations to build circuitry. Lot scheduling is an important task for manufacturers in order to improve production efficiency and satisfy customers’ demands of on-time delivery. Cycle time and average work-in-process reduction while meeting customers’ requirements play an important role in improving the competitiveness and sustainability of a semiconductor manufacturer. In this research, we propose the optimal combination rules for lot scheduling problems in wafer fabs, focusing on three complex areas of decision making: lot release control, batch sizing, and dispatching lots to enhance competitiveness and sustainability of a semiconductor facility.

The accuracy of maxillary positioning using digital model planning and 3D printed wafers in bimaxillary orthognathic surgery.

Orthognathic wafers may be made using digital model movements and CAD-CAM technology. This paper analysed the accuracy of maxillary movements using this new process. Retrospective study of pre and post-operative cephalograms. Thirty consecutive orthognathic patients undergoing bimaxillary osteotomies in a UK hospital. Jaw movements were planned using cephalometric and Orthoanalyzer™ software. The resultant intermediate and final wafer occlusal relationships were used for wafer fabrication by 3D printing of the inter-occlusal space. Pre- and post-operative lateral cephalograms were compared in terms of maxillary antero-posterior and vertical movements. Statistical analyses including the paired t-test, two-sample t-test and Fisher's exact test. Wide individual variation was observed between the planned and actual movements. Thirteen cases (43%) had a 2 mm discrepancy in at least one variable. Statistically significant differences between the planned and actual maxillary vertical movements were observed for the molar (U6y: p < 0.0001) and anterior maxillary (Ay: p < 0.01) differences. Analysis of a subgroup with primarily impaction movements demonstrated a statistically significant bias towards excessive maxillary advancement (U1x: p < 0.01) and incisor impaction (U1y: p < 0.01) in this group. This new digital surgical wafer technique achieves a similar level of accuracy to the conventional facebow and model surgery process.

Completion Time Analysis of Wafer Lots in Single-Armed Cluster Tools With Parallel Processing Modules

We analyze the completion time of wafer lots in single-armed cluster tools with parallel processing modules (PMs) by considering the lot switching operation. To effectively assign wafer lots and dispatch overhead hoist transports (OHTs) to manufacturing tools, it is crucial to obtain the completion time of wafer lots. However, estimating the completion time is not straightforward, due to the concurrent processing of two consecutive wafer lots during lot switching operation, which often increases wafer sojourn times in PMs. In this paper, we derive closed-form expressions of the completion time of wafer lots in single-armed cluster tools with parallel PMs. We assume that the robot unloads wafers in the order of their loading sequence. We then experimentally show that the formulas derived can be used even when processing time variation exists or another robot task sequence, which is of first-in first-out (FIFO), is assumed. Note to Practitioners —Due to the larger wafer size and circuit width reduction, cluster tools often perform the lot switching operation with each pair of consecutive wafer lots. In addition, since most tools are operated with parallel chambers, concurrent processing with two different wafer lots occurs frequently. Such transient periods in operating tools make it hard to estimate the completion time of wafer lots. In this paper, we derive closed-form expressions to obtain the completion time of wafer lots in single-armed cluster tools with parallel chambers. We further show that the formulas can be used with processing time variation or the FIFO rule. With the formulas, OHTs can be sent just-in-time to tools to load or unload wafer cassettes, and wafer lots can be assigned while minimizing the transient periods. In addition, the estimated completion time can be utilized in the planning and scheduling of wafer fabrication processes.

Crack detection in crystalline silicon solar cells using dark-field imaging

The high capital expenditure (capex) necessary to manufacture crystalline silicon PV modules negatively affects the levelized cost of electricity (¢/kWh) and critically impacts the rate at which the PV industry can scale up. Wafer, cell, and module fabrication with thin free-standing silicon wafers is one key to reduce capex. Thin wafers reduce capex associated with silicon refining and wafer fabrication, which together sum to 58% of the total capex of silicon module manufacturing. In addition, thin wafers directly and significantly reduce variable costs. However, introducing 50 μm thin free-standing wafers into today’s manufacturing lines result in cracking, creating a yield-based disincentive. Due to the brittle nature of silicon, wafer breakage is the major concern due to the high stress that is induced during processes in manufacturing lines. In this paper, we describe an improved method for edge micro-crack detection that can help enable low-capex, thin free-standing Si wafers. We present a method of detecting and measuring cracks along wafer edges by using a dark-field IR scattering imaging technique which enables detection of edge cracks at the micron scale.

(Invited) SiGe BiCMOS Heterogeneous Integration Using Wafer Bonding Technologies

Heterogeneous integration has been a very attractive research topic for the last decades. Due to the limitations for further device scaling the More-than-Moore approach based on heterogeneous integration has been pointed out as the key integration path for future smart system integration [1]. Temporary and permanent wafer bonding technologies are one of the key enabling technologies for heterogeneous integration. Temporary wafer bonding is a well-established bonding technique to provide a stable handling and fabrication of ultra-thin silicon wafers. Permanent wafer bonding with various electrical isolating or conductive bonding interfaces is applied for wafer-level heterogeneous device integration [2]. Making available both temporary and permanent wafer bonding technologies together with a high performance SiGe BiCMOS technology will pave the way for new applications like millimeter-wave packaging, 3D-integration and smart sensors to realize multi-functional and miniaturized systems. The potential of temporary and permanent wafer bonding techniques for heterogeneous integration of a high performance SiGe BiCMOS technology with additional devices and technology modules will be presented by three different application examples namely BiCMOS embedded Through-Silicon Vias (TSV), silicon interposer including substrate-integrated waveguides and BiCMOS embedded microfluidics. With respect to the different applications the potential and the main technology obstacles for SiGe BiCMOS temporary and permanent wafer bonding will be highlighted. While the temporary wafer bonding process with subsequent wafer thinning and thin wafer backside fabrication is mainly limited by the robustness of adhesives against high temperature and high vacuum process conditions, the permanent wafer bonding based on SiO2-SiO2 fusion bonding is mainly limited by the demanding surface requirements in terms of roughness and wafer bow which has been optimized to fulfill the requirements. By optimizing the SiGe BiCMOS technology both temporary and permanent wafer bonding together with subsequent semiconductor fabrication becomes feasible. In summary, the development of wafer bonding application together with an industrial-level BiCMOS process will be presented. By the use of temporary and permanent wafer bonding new applications in the area of heterogeneous integration becomes feasible making SiGe BiCMOS technologies more attractive for future smart system applications.

A Performance Driven Lot Merging Method with Closed Loop Optimization for Semiconductor Wafer Fabrication

A Performance Driven Lot Merging Method with Closed Loop Optimization for Semiconductor Wafer Fabrication

(Invited) 650 Volt GaN Commercialization Reaches Automotive Standards

1. Introduction With its proven ability to reduce size (form factor) and save energy (high efficiency) Gallium Nitride (GaN) is now no longer a nice to have, it is a must-have for power conversion. In applications ranging from sub 100 watt to multi kilowatt highly efficient power converters and inverters, GaN HEMTs high switching speed and low efficiency make it a natural choice of Silicon based devices reaching their physical limits of performance. Transphorm has already commercialized JEDEC qualified GaN HEMT power switches manufactured in an automotive grade 6 inch Si CMOS fab [1]. With this strong base and its ability to reduce size, weight and improve miles per gallon, GaN HEMTs are now increasingly being investigated for EV & HEV applications such as on board chargers and other auxiliary power conversion within the automobile under 10 kW. We will review the first ever Automotive (AEC Q101) Qualification for GaN and also discuss results for highly stressed robustness tests, FIT rates & lifetime testing. 2. GaN Products and Qualification Normally off GaN devices (Fig. 1) are achieve through integration of a low voltage Si-MOSFET input device with a high voltage depletion mode GaN device offering the best combination of input gate interface and the most robust high voltage GaN platform [2]. Electrical characteristics of the normally-off GaN power switch are summarized in Table 1 with a Low Rds(on), low gate charge (Qg) and low capacitance (Coss) that enable high efficiency, small form factor power systems. The Ron *Qg or Ron * Coss figure of merit is already better than mature Silicon Superjunction MOSFETs and achieved simultaneously with superior reliability performance. We have successfully passed (on multiple products and generations) the full suite of JEDEC qualification tests [3], as shown in Table 2. 3. Robustness, Long Term Reliability and Lifetime of High Voltage GaN To further establish confidence in long term reliability and operation in the field with low FIT rates, we have extended JEDEC qualification to 3-5x the stresses, for e.g. 5,000 hours of HTRB (5x JEDEC stress) with no degradation in resistance, threshold or leakage (Fig 3). Systematic high voltage off-stage (HVOS) acceleration at over 1100 volts was done to determine intrinsic lifetime (MTTF) of over 100 Million hours and 1% failure of more than 1M hours (Fig 5). Similarly through accelerated high temperature on-state testing of GaN, a high temperature MTTF of over 100 Million hours at 175C was determined. Recently, in March 2017, we completed the first ever successful AEC-Q101 standard qualification of GaN products [4]. These will be discussed in detail at the conference. 4. GaN Products and Qualification The comprehensive suite of data and results with a 3 year manufacturing history on over 3,000 wafers in a high volume commercial 6-inch Wafer fabrication facility unequivocally demonstrate that GaN power switches are now reliable and ready for a wide array of consumer & communication, industrial & renewable energy as well as automotive applications. The next milestones which are now happening include announcement of a variety of end system products (Titanium rated data server power supplies, PV Inverters, Telecom power supplies and Servo motor drives), paving the way for an exciting era in highest efficiency, highest reliability power conversion with GaN.5. References P. Parikh, et. al., “Commercialization of 600V GaN HEMTs,” 2014 SSDM, Tsukuba, Sep., 2014. Power GaN Devices- Materials, Applications and Reliability, Edited by M. Meneghini et. al., Springer International Publishing, 2017. T. Kikkawa, et al. 600 V JEDEC-Qualified Highly Reliable GaN HEMTs on Si Substrates,” IEEE IEDM, San Francisco, Dec. 2014. APEC 2017, http://www.transphormusa.com/news/transphorm-announces-first-automotive-qualified-gan-fets/ Figure 1

Scheduling Transient Processes for Time-Constrained Single-Arm Robotic Multi-Cluster Tools

Multi-cluster tools are highly productive yet expensive wafer fabricating facility in semiconductor industry. Current competitive business trend requires high-mix and low-volume production of wafers. The size of a wafer lot is becoming smaller and wafer lots change more frequently. This brings up with many start-up and close-down processes. It is thus more and more important to control these transient processes to ensure the highest utilization of expensive facility. Since many wafer fabrication processes have strict residency time constraints after a wafer’s processing, this work aims to schedule optimally the transient processes of single-arm multi-cluster tools subject to such constraints. For such tools whose optimal steady state schedules can be found, we propose linear programs to find the optimal schedules for start-up and close-down processes for the first time. The obtained schedules make the transitions between transient and steady states seamlessly. Examples are presented to illustrate how the proposed method outperforms the existing ones by about 10% throughput.

A Testbed for Simulating Semiconductor Supply Chains

In this paper, a supply chain simulation testbed for the semiconductor industry is proposed. We start by identifying requirements for such reference datasets, and then we identify the main building blocks. The nodes of the supply chain that represent semiconductor wafer fabrication facilities (wafer fabs) are built on a simulation model from the measurement and improvement of manufacturing capacity project. We present two techniques to reduce the modeling and computational burden that are able to deal with load-dependent cycle times in single front-end and back-end facilities and in the overall network. The first method models in detail only the bottlenecks in the nodes of the supply chain, while the second one uses empirical distributions for cycle time and throughput. The quality of these reduction techniques is assessed by comparing the detailed model and the models with a reduced level of detail. We present an application scenario for the testbed by simulating a semiconductor supply network. In addition, the usage of the testbed is discussed.

An Improved Dispatching Method (a-HPDB) for Automated Material Handling System with Active Rolling Belt for 450 mm Wafer Fabrication

The semiconductor industry is facing the transition from 300 mm to 450 mm wafer fabrication. Due to the increased size and weight, 450 mm wafers will pose unprecedented challenges on semiconductor wafer fabrication. To better handle and transport 450 mm wafers, an advanced Automated Material Handling System (AMHS) is definitely required. Though conveyor-based AMHS is expected to be suitable for 450 mm wafer fabrication, still it faces two main problems, traffic-jam problem and lot-prioritization. To address the two problems, in this research we have proposed an improved dispatching method, termed Heuristic Preemptive Dispatching Method using Activated Roller Belt (a-HPDB). We have developed some effective rules for the a-HPDB based on Activated Roller Belt (ARB). In addition, we have conducted experiments to investigate its effectiveness. Compared with the HPDB and R-HPD, two dispatching rules proposed in previous studies, our experimental results showed the a-HPDB had a better performance in terms of average lot delivery time (ALDT). For hot lots and normal lots, the a-HPDB had advantages of 4.14% and 8.92% over the HPDB and advantages of 4.89% and 8.52% over R-HPD, respectively.

A discrete spatial model for wafer yield prediction

ABSTRACTYield analysis is one of the key concerns in the fabrication of semiconductor wafers. An effective yield analysis model will contribute to production planning and control, cost reductions and the enhanced competitiveness of enterprises. In this article, we propose a novel discrete spatial model based on defect data on wafer maps for analyzing and predicting wafer yields at different chip locations. More specifically, based on a Bayesian framework, we propose a hierarchical generalized linear mixed model, which incorporates both global trends and spatially correlated effects to characterize wafer yields with clustered defects. Both real and simulated data are used to validate the performance of the proposed model. The experimental results show that the newly proposed model offers an improved fit to spatially correlated wafer map data.

Group‐III Sesquioxides: Growth, Physical Properties and Devices

The group‐III sesquioxides possess material properties that render them interesting for applications such as high‐power rectifiers and transistors, solar‐blind UV detectors and inter‐sub‐band infrared detectors. Technology for growing large, single‐crystalline bulk material and for wafer fabrication exists, enabling homoepitaxial growth of thin films with high crystalline quality. The bandgap can be tuned in an energy range from about 4 to 8 eV for the ternary alloys and allows growth of heterostructures with large band offset. Here, past results and recent investigations on the growth, the material properties, contact fabrication and the alloying of group‐III sesquioxides are reviewed, and an overview on demonstrator devices is provided.

Scheduling and Control of Startup Process for Single-Arm Cluster Tools With Residency Time Constraints

Due to the trends of larger wafer diameters and smaller lot sizes, cluster tools need to switch from processing one lot of wafers to another frequently. This leads to more transient periods in wafer fabrication, which includes startup and close-down processes. Their efficient scheduling and control problems become more and more important. They become very difficult to solve especially when wafer residency time constraints must be considered. Most previous studies focused on the steady periodic schedule for cluster tools. Little research was on the transient processes of cluster tools despite their increasing importance. In order to optimize a startup transient process, this work develops a Petri net model to describe its behavior for a single-arm cluster tool. Then, based on the model, for the case that the workloads among the steps can be properly balanced, this work proposes a scheduling algorithm to find an optimal and feasible schedule for the startup process. For the other cases schedulable at the steady state, a linear programming model is developed to find an optimal and feasible schedule for the startup process. Finally, illustrative examples are given to show the applications of the proposed method.

Binary Phase Diagrams and Thermodynamic Properties of Silicon and Essential Doping Elements (Al, As, B, Bi, Ga, In, N, P, Sb and Tl).

Fabrication of solar and electronic silicon wafers involves direct contact between solid, liquid and gas phases at near equilibrium conditions. Understanding of the phase diagrams and thermochemical properties of the Si-dopant binary systems is essential for providing processing conditions and for understanding the phase formation and transformation. In this work, ten Si-based binary phase diagrams, including Si with group IIIA elements (Al, B, Ga, In and Tl) and with group VA elements (As, Bi, N, P and Sb), have been reviewed. Each of these systems has been critically discussed on both aspects of phase diagram and thermodynamic properties. The available experimental data and thermodynamic parameters in the literature have been summarized and assessed thoroughly to provide consistent understanding of each system. Some systems were re-calculated to obtain a combination of the best evaluated phase diagram and a set of optimized thermodynamic parameters. As doping levels of solar and electronic silicon are of high technological importance, diffusion data has been presented to serve as a useful reference on the properties, behavior and quantities of metal impurities in silicon. This paper is meant to bridge the theoretical understanding of phase diagrams with the research and development of solar-grade silicon production, relying on the available information in the literature and our own analysis.

A hybrid scheduling approach for a two-stage flexible flow shop with batch processing machines

In this paper, we discuss a flexible flow shop scheduling problem with batch processing machines at each stage and with jobs that have unequal ready times. Scheduling problems of this type can be found in semiconductor wafer fabrication facilities (wafer fabs). We are interested in minimizing the total weighted tardiness of the jobs. We present a mixed integer programming formulation. The batch scheduling problem is NP-hard. Therefore, an iterative stage-based decomposition approach is proposed that is hybridized with neighborhood search techniques. The decomposition scheme provides internal due dates and ready times for the jobs on the first and second stage, respectively. Each of the resulting parallel machine batch scheduling problems is solved by variable neighborhood search in each iteration. Based on the schedules of the subproblems, the internal due dates and ready times are updated. We present the results of designed computational experiments that also consider the number of machines assigned to each stage as a design factor. It turns out that the proposed hybrid approach outperforms an iterative decomposition scheme where a fairly simple heuristic based on time window decomposition and the apparent tardiness cost dispatching rule is used to solve the subproblems. Recommendations for the design of the two stages with respect to the number of parallel machines on each stage are given.

An Effective Approach for Associating the Sources of Defect Signatures to Process Zones

A semiconductor wafer undergoes various processing steps before it is transformed from a plain silicon wafer to one populated with thousands of integrated circuits. Each of these processing steps is susceptible to specific types of defects. Some defects may not be captured by in-line inspection tools or may not be sampled during defect review-scanning electron microscope and are carried over multiple processing steps. Such defects can be discovered at the end of the fabrication procedure, which requires process engineers to trace back the manufacturing processes that caused these defects. Despite the success of most current methods that detect defects during wafer fabrication, most of these methods are inable to accurately associate the source of an individual defect type to a specific semiconductor processing step. We believe that this limitation can be overcome by considering the carry-over of defect signatures rather than individual defects. We propose in this paper a system called step-defect contribution analyzer (SDCA) that detects defect signatures on semiconductor wafers and overcomes the limitations outlined above. SDCA allows process engineers to trace back and associate the source of a final defectivity discovered at the end of the fabrication procedure to specific defect signatures carried over multiple process zones. We experimentally evaluated the quality of SDCA by measuring its prediction accuracy. Results revealed marked prediction accuracy.

Real-time OHT Dispatching Mechanism for the Interbay Automated Material Handling System with Shortcuts and Bypasses

As a key to improve the performance of the interbay automated material handling system (AMHS) in 300 mm semiconductor wafer fabrication system, the real-time overhead hoist transport (OHT) dispatching problem has received much attention. This problem is first formulated as a special form of assignment problem and it is proved that more than one solution will be obtained by Hungarian algorithm simultaneously. Through proposing and strictly proving two propositions related to the characteristics of these solutions, a modified Hungarian algorithm is designed to distinguish these solutions. Finally, a new real-time OHT dispatching method is carefully designed by implementing the solution obtained by the modified Hungarian algorithm. The experimental results of discrete event simulations show that, compared with conventional Hungarian algorithm dispatching method, the proposed dispatching method that chooses the solution with the maximum variance respectively reduces on average 4 s of the average waiting time and average lead time of wafer lots, and its performance is rather stable in multiple different scenarios of the interbay AMHS with different quantities of shortcuts. This research provides an efficient real-time OHT dispatching mechanism for the interbay AMHS with shortcuts and bypasses.