Wafer Fabrication Factory Research Articles

An iterative cutting procedure for determining the optimal wafer exposure pattern

Conventionally, people focus on defect reduction to improve yield rate. Little research has been done to deal with the problem of optimizing wafer exposure patterns. This paper develops a computer-based procedure to maximize the number of dies possibly produced from a wafer. A program has been developed and implemented in a 6-in wafer fabrication factory in Taiwan. The results validate the practical viability of the proposed procedure.

The design of due date assignment model and the determination of flow time control parameters for the wafer fabrication factories

High work-in-process (WIP) level, long manufacturing lead time, high lead time variation, and poor due date performance are the major problems for wafer fabrication factories. An order's due date relates to its releasing time and flow time. Due date performance will not be improved if WIP level is high and material flow is unstable. Too high WIP level cannot increase throughput but lengthens lead time. Find a suitable WIP level and then control the material release by fixed-WIP policy. In this paper, we construct a due date assignment model (DDAM) by using the simulation method and queuing theory. Observing the results of simulations, the lowest system WIP level corresponding to the desired up-time machine utilization rate of the bottleneck resource or the capacity constraint resource (CCR) and the shortest mean flow time can be found. To make the material flow stable, we also propose the methodology of determining a wafer's WIP level, daily moves, and flow time for each product type and for each circuitry layer; all of these can be used as the parameters for controlling flow time. Demonstration of the DDAM is provided with actual data. Comparing the performance of our DDAM with others, the results reveal that DDAM performs well in each performance criterion.

Shop floor control in computer-integrated manufacturing for large-scale integrated wafer fabrication systems

Manufacturing technology in the field of Large-Scale-Integrated (LSI) circuit production has overcome the problems of enlarged wafer size and increasing level of integration. The market environment of the LSI industry has become more demanding with increased requirements, delivery time and stiffer cost competition. A Computer-Integrated Manufacturing System (CIMS) well-adapted to the unique characteristics of LSI production system is thus urgently needed. This paper describes the development of CIMS in LSI production systems, and presents the example of a DTS (Diffusion Total System), constructed in a real LSI wafer fabrication factory. Features of DTS are (a) on-line real-time manufacturing data acquisition and monitoring through a production information network, (b) automatic control of process equipment, (c) shop floor control for computer aided decision support at the shop floor level, and (d) data analysis and reporting derived from a large amount of accumulated data. This paper deals with shop floor control, and in particular with a priority control system unique to the LSI wafer fabrication line.

Development of On-Line, Real-Time, Scheduling Method for a Computer Aided Manufacturing System

This paper describes the development of an on-line, real-time, scheduling method for a computer aided manufacturing system and relates one application example in LSI wafer fabrication factory. Features of the scheduling method are: (1) it is a dynamic, work-in-process scheduler based on job shop simulation techniques and a priority function having weighted decision factors, (2) it can automatically generate the optimum launching sequence of jobs on a machine, as soon as the system situation changes, (3) it is a multi-purpose scheduler in that it uses an objective function which is a linear combination of several decision factors which suits the system environment by modifying the coefficients that define the relative importance, (4) the complexity of the job shop configuration does not affect the size of scheduling problem.