The design of due date assignment model and the determination of flow time control parameters for the wafer fabrication factories

Abstract

High work-in-process (WIP) level, long manufacturing lead time, high lead time variation, and poor due date performance are the major problems for wafer fabrication factories. An order's due date relates to its releasing time and flow time. Due date performance will not be improved if WIP level is high and material flow is unstable. Too high WIP level cannot increase throughput but lengthens lead time. Find a suitable WIP level and then control the material release by fixed-WIP policy. In this paper, we construct a due date assignment model (DDAM) by using the simulation method and queuing theory. Observing the results of simulations, the lowest system WIP level corresponding to the desired up-time machine utilization rate of the bottleneck resource or the capacity constraint resource (CCR) and the shortest mean flow time can be found. To make the material flow stable, we also propose the methodology of determining a wafer's WIP level, daily moves, and flow time for each product type and for each circuitry layer; all of these can be used as the parameters for controlling flow time. Demonstration of the DDAM is provided with actual data. Comparing the performance of our DDAM with others, the results reveal that DDAM performs well in each performance criterion.