Wafer Cost Research Articles

Estimation of Influence on Carbon Vacancy Regarding 4H-SiC Substrate Grown by HTCVD Method

In order to increase productivity and reduce the cost of wafers, we have developed a high temperature chemical vapor deposition (HTCVD) method that can realize the high-speed growth of 4H-SiC crystals. Tokuda et al. reported an interesting study in which the carrier lifetime of a substrate grown by HTCVD (HTCVD substrate) was considerably shorter than that of the substrate grown by physical vapor transport (PVT); moreover, bipolar degradation was highly suppressed when the HTCVD substrate was applied to PiN diodes [1]. Herein, we demonstrate that the short carrier lifetime of the HTCVD substrate is mainly attributable to the carbon vacancy (VC) and that VC particularly diffuses from the HTCVD substrate to the epitaxial layer.

High-density Fan-Out Chip on Substrate using M-Series (TM) and Adaptive Patterning® Technology

As silicon technology nodes advance and wafer costs increase, there is a strong incentive to shrink die size and concurrently, die pad pitch. This increased density typically drives higher cost advanced substrates with finer lines and spaces and potentially more layers. As a result of recent constraints on the substrate supply chain, this creates serious availability and cost concerns. A compelling solution is to use fan-out on substrate technology to increase the effective die pad pitch, allowing the use of simpler, lower layer count substrates. ASE used this single die Fan Out Chip on Substrate (FOCoS) approach in engineering and qualification builds starting in 2017 with a traditional fan-out solution. However, with increasing interconnect density, the conventional approach is limited in its ability to work with small bond pad pitches as the die shift during molding creates challenges for manufacturing. An oversized capture pad is often utilized to accommodate this shift and in one prominent case, an additional Cu layer is required. M-series’ use of Adaptive Patterning eliminates the need for oversized capture pads through a unique design-during-manufacturing process which precisely aligns the package interconnect layers to the actual location of each die after molding. This paper will examine the design and manufacturing of a FOCoS package using 4nm silicon through the cooperation of Deca and ASE. The design fans out the interface of a 12mm x 12mm die with 6,000 IO using a single RDL layer and 5 µm line and space. The die has a core pitch of 150µm with an average periphery pitch of 90µm. The resultant M-series flip-chip bumps have a core pitch of 150µm over 75% of the die area with a secondary pitch of 212µm encompassing the remaining perimeter of the die and the 30% body size growth provided by the fan-out region. The relaxed pitch provided by M-series fan-out opens the possibility to use the most cost-effective, readily available type of laminate substrate.

Learning from single-defect wafer maps to classify mixed-defect wafer maps

Automation of wafer map pattern classification has been an active research topic for identifying the root causes of semiconductor manufacturing processes. Building a classification model is a primary challenge owing to the high cost of labeling wafer maps with their defect categories to create a training dataset. Single-defect wafer maps are relatively easy to label because their patterns are simple and clear. However, labeling mixed-defect wafer maps is difficult and time-consuming because they often have complex and ambiguous patterns. This study aims to address the problem of data insufficiency in which only normal and single-defect wafer maps are present in the training dataset, whereas mixed-defect wafer maps are also present in the test dataset. We propose a method for training a convolutional neural network (CNN) by using a training dataset of normal and single-defect wafer maps to accurately classify mixed-defect wafer maps. The proposed method utilizes three components to generate synthetic wafer maps from the training dataset: mixup, random rotation, and noise filtering. Mixup combines single-defect wafer maps to create synthetic mixed-defect wafer maps. Random rotation increases the diversity of the synthetic wafer maps. Noise filtering prevents the accumulation of random noise in synthetic wafer maps. The CNN is trained with the synthetic wafer maps generated through the proposed method, which include normal, single-defect, and mixed-defect variations. Through experimental investigation using the MixedWM38 dataset, we demonstrate that the proposed method significantly outperforms the existing methods.

Heteroepitaxial growth of GaSb interfacial misfit array on GaAs substrate by molecular beam epitaxy

Heteroepitaxy growth of antimonide-based superlattices offers new opportunities for band structure engineering in infrared optoelectronics. Due to the wafer size limitations and cost of GaSb substrates, lattice − mismatched epitaxy of antimonide-based materials on GaAs substrates presents an attractive alternative with large wafer scales, low costs, and great ohmic contacts. Herein, we report a heterostructure growth method using molecular beam epitaxy based on the interfacial misfit (IMF) array technique. The 7.8% lattice mismatch at the GaAs/GaSb interface was accommodated through a thin low temperature (LT) nucleation layer followed by a thick high-temperature (HT) GaSb buffer layer. We explain the evolution of rectangular-like defects for direct growth GaSb on GaAs substrates. Under optimized GaAs/LT-GaSb/GaSb heterostructure growth conditions, we achieved highly smooth GaSb surfaces with well-defined atomic steps as observed in atomic force microscope (AFM) measurements. Furthermore, high-resolution X-ray diffraction (HRXRD) characterization reveals that misfit dislocations are dominated by 90° dislocations at the GaAs/GaSb interface. We obtained a full width at half maximum (FWHM) of 140.6 arcsec for a 2 μm thick GaSb layer on a GaAs substrate and achieved a high lattice relaxation of 99.7%. These results demonstrate that our proposed growth method holds great potential for achieving excellent surface morphology and high crystal quality in GaAs/GaSb heteroepitaxial system.

Application of computer modeling to pulling rate and productivity of Czochralski pullers in PV Si crystal growth

More than 30 billion silicon wafers are produced each year for solar industry. To satisfy market demand and increase market share, manufacturers of monocrystalline ingots/wafers need to actively work on technology improvements to gain competitive advantage. Optimization of production technology of silicon crystals is essential in enhancing PV conversion efficiency and reducing cost per watt, which are the core competitiveness in solar industry. One of the most powerful ways of technology optimization in these directions is increasing the crystal pulling rate of Czochralski pullers. Computer modeling has become one of the main tools for optimizing crystal growth technology in industry. In this paper, we present the simulation capabilities to analyze the effect of the hot zone design on the possibility of increasing the growth rate of silicon crystals both for standard diameter of 8.5 in. and for the next-generation crystals for solar cells with diameters up to 12 in.. Modeling results have been verified in the pilot and mass production facilities, thus confirming the accuracy of computations, and providing opportunities to reduce the cost of silicon wafer and solar cell production.

Improvement of the signal to noise ratio for fluorescent imaging in microfluidic chips

Microfluidics systems can be fabricated in various ways using original silicon glass systems, with easy Si processing and surface modifications for subsequent applications such as cell seeding and their study. Fluorescent imaging of cells became a standard technique for the investigation of cell behavior. Unfortunately, high sensitivity fluorescent imaging, e.g., using total internal reflection fluorescence (TIRF) microscopy, is problematic in these microfluidic systems because the uneven surfaces of the silicon channels’ bottoms affect light penetration through the optical filters. In this work, we study the nature of the phenomenon, finding that the problem can be rectified by using a silicon-on-insulator (SOI) substrate, defining the channel depth by the thickness of the top Si layer, and halting the etching at the buried SiO2 layer. Then the fluorescent background signal drops by = 5 times, corresponding to the limit of detection drop from = 0.05 mM to = 50 nM of fluorescein. We demonstrate the importance of a flat surface using TIRF-based single-molecule detection, improving the signal to a noise ratio more than 18 times compared to a conventional Si wafer. Overall, using very high-quality SOI substrates pays off, as it improves the fluorescence image quality due to the increase in signal-to-noise ratio. Concerning the cost of microfluidic device fabrication—design, mask fabrication, wafer processing, and device testing—the initial SOI wafer cost is marginal, and using it improves the system performance.

High Lifetime Ga‐Doped Cz‐Si for Carrier‐Selective Junction Solar Cells

Industrial mass production of solar cells is at a transition toward carrier‐selective junction solar cells with passivating contacts such as TOPCon, POLO, or heterojunction technology (HJT). At the same time, many manufacturers consider switching from p‐type Cz‐Si to n‐type Cz‐Si wafers. This contribution indicates that Ga‐doped p‐type Cz‐Si material is still a viable option for the new type of devices while giving an opportunity to benefit from lower wafer cost. The minority carrier diffusion lengths that are an order of magnitude larger than the thickness of the studied HJT and TOPCoRE devices are reported. Stability aspects for operation in the field are discussed. Best TOPCoRE solar cells on Ga‐doped Cz‐Si show a 0.2% higher efficiency than their co‐processed n‐type counterparts.

Status and perspectives of crystalline silicon photovoltaics in research and industry

Crystalline silicon (c-Si) photovoltaics has long been considered energy intensive and costly. Over the past decades, spectacular improvements along the manufacturing chain have made c-Si a low-cost source of electricity that can no longer be ignored. Over 125 GW of c-Si modules have been installed in 2020, 95% of the overall photovoltaic (PV) market, and over 700 GW has been cumulatively installed. There are some strong indications that c-Si photovoltaics could become the most important world electricity source by 2040–2050. In this Review, we survey the key changes related to materials and industrial processing of silicon PV components. At the wafer level, a strong reduction in polysilicon cost and the general implementation of diamond wire sawing has reduced the cost of monocrystalline wafers. In parallel, the concentration of impurities and electronic defects in the various types of wafers has been reduced, allowing for high efficiency in industrial devices. Improved cleanliness in production lines, increased tool automation and improved production technology and cell architectures all helped to increase the efficiency of mainstream modules. Efficiency gains at the cell level were accompanied by an increase in wafer size and by the introduction of advanced assembly techniques. These improvements have allowed a reduction of cell-to-module efficiency losses and will accelerate the yearly efficiency gain of mainstream modules. To conclude, we discuss what it will take for other PV technologies to compete with silicon on the mass market.

Wire-bow in situ measurements for powerful control of wire-wear during diamond-wire crystalline silicon sawing.

Original instrumental setups embedded in industrial-type multi-diamond-wire sawing equipment are presented for in situ measurements of the apparent wire diameter, the vertical force applied to the wire web, and the wire-web bow during the cutting of crystalline silicon bricks into wafers. The proportionality relationship between the vertical force and the wire bow during the cut of a Czochralski silicon brick is, for the first time, experimentally observed as expected by the theoretical calculations. As a result, the in situ bow measurement is shown to provide a direct control of the cutting efficiency, which is inversely proportional to the vertical force. In addition, the wire-wear evolution during successive cuts is analyzed using the in situ measurement of the apparent wire diameter together with the in situ bow measurements for equivalent cutting conditions using several bow sensors distributed above the wire web. The three-dimensional plot of the cutting efficiency resulting from the bow measurement processing gives access to the distribution of the cutting efficiency along the wire web during the progress of the cut. Given the homogeneous properties of the silicon material used, the cutting efficiency proves to be a representative of the wire-wear. Moreover, the unique capability of the in situ bow measurement to provide a distribution of the measurements on the wire web during the cut allows studying the wire web behavior and the wire cutting efficiency distribution for different cutting conditions. Thanks to the innovative design of the instrumentation coupled with a data analysis based on a deep understanding of the involved physical phenomena, the in situ bow measurement is demonstrated to be a powerful tool to optimize the cutting process in terms of wafer quality and cost efficiency. Moreover, it can provide real-time information opening the door for tuning the parameters during the cutting process.

Ultrasensitive Self-Powered Position-Sensitive Detector Based on n-3C-SiC/p-Si Heterojunctions

Cubic silicon carbide (3C-SiC) on silicon (Si) is an excellent platform for developing sensors that can function in a harsh environment due to its superior mechanical, electrical, chemical, optoelectronic properties and low wafer cost. Here, we report a position-sensitive detector (PSD) based on the heterojunction formed between n-type SiC and p-type Si. The PSD utilizes the lateral photovoltaic effect (LPE) with a linear dependence of LPE on laser spot positions. The position sensitivity is found to be 554.82 mV/mm at zero bias conditions under an illumination of 200 μW (637 nm), which is among the most sensitive LPE-based PSDs to date. The generation of the lateral photovoltage (LPV) under light illumination is investigated by examining the band diagram of the 3C-SiC/Si heterojunction. The influence of the illumination intensity and wavelength on the position sensitivity is also explained. This work demonstrates a potential application for ultrasensitive, self-powered optoelectronic sensing of the n-3C-SiC/p-Si platform.

Growth of bulk single crystal ScAlMgO4 boules and GaN films on ScAlMgO4 substrates for GaN-based optical devices, high-power and high-frequency transistors

Single crystal growth of ScAlMgO4 boules with 10 mm up to 4 in. (c.a. 101.6 mm) in diameter by Czochralski technique was demonstrated. Some high quality ScAlMgO4 single crystal boules with 2-inches (c.a. 50.8 mm) in diameter were successfully grown without dislocation, which was revealed by X-ray rocking curve and X-ray topography measurements for the c-plane wafers. After a GaN template was formed on a substrate cut out from a grown ScAlMgO4 boule by using metalorganic vapor phase epitaxy, a thick GaN film was epitaxially grown on the template using hydride vapor phase epitaxy (HVPE). At the cooling stage after the growth in the HVPE process, the thick grown GaN film was separated by itself from the ScAlMgO4 substrate due to high cleavability of ScAlMgO4, which makes it possible the reuse of the substrate. The free-standing GaN grown on the reused ScAlMgO4 substrate showed the same quality as a GaN fabricated on a fresh ScAlMgO4 substrate. The reuse of ScAlMgO4 substrates is beneficial for saving the GaN films fabrication cost. The fabrication of a free-standing GaN substrate with 2 in. in diameter and 1 mm in thickness on ScAlMgO4 substrates was demonstrated to be more high-yield than the fabrication on a sapphire substrate. The growth method shown in this study is very promising, and it opens an efficient way to obtain GaN free-standing wafers and to reduce the production cost of GaN wafers.

Design guidelines for a highly efficient high-purity germanium (HPGe)-based double-heterojunction solar cell

Despite having higher carrier mobilities and absorption coefficients of germanium (Ge) than those of silicon (Si), there has been less focus on Ge-based solar cells due to the low bandgap and high cost of Ge wafer as well as the requirement of its high-purity level. Currently, the availability of high-purity Ge (HPGe), the low-cost wafer slicing method, and proper design guidelines make it possible to design HPGe-based solar cells. Accordingly, in this article, we have designed and simulated a novel n-CdS/p-HPGe/p+-BaSi2 based npp+ double-heterojunction solar cell (DHJSC), where HPGe, cadmium sulfide (CdS), and orthorhombic barium disilicide (β-BaSi2) have been used as the absorber, window, and back-surface field (BSF) layers, respectively. Using the solar cell capacitance simulator (SCAPS-1D), the effects of different physical parameters such as the thickness, doping, and defect densities, band offsets, and temperature on the photovoltaic (PV) parameters of the designed solar cells have been investigated systematically. This article renders the optimized PV parameters to improve the device performance with the highest power conversion efficiency (PCE) of ∼45.65% with a high open-circuit voltage of 1.16 V owing to the high built-in voltage of 1.7 V for the n-CdS/p-HPGe/p+-BaSi2 solar cells. This efficiency is almost consistent with the detailed balance limit for DHJSCs.

Epitaxial Ge-Gd[formula omitted]O[formula omitted] on Si(111) substrate by sputtering for germanium-on-insulator applications

Germanium-on-insulator (GeOI) technology is a potential-alternative to the bulk-silicon based devices for radio-frequency (RF), and complementary metal oxide semiconductor applications at advanced technology nodes. A thin germanium channel is the key enabler of high mobility transistors and group-IV photonic devices. A prohibitive cost of GeOI wafers may discourage high volume manufacturing (HVM) despite promising performance. Here, we demonstrate epitaxial Gd2O3-Ge-Gd2O3 thin film growth on Si(111) substrate in an HVM platform - RF magnetron sputter system, where, the first Gd2O3 layer acts as buried-oxide (BOX) in the GeOI wafer. The second Gd2O3 layer is used as a cap-layer to be removed later using wet etching. Both the Gd2O3 layer is grown epitaxially at 750∘C, while the germanium layer is grown at room temperature and crystallised later by solid phase epitaxy (SPE) technique. The entire growth is performed without vacuum-break, to enable high throughput and excellent interface control. To compare the quality of the heterostructure, this sputter based SPE is performed on: (1) in-situ sputter grown, versus (2) ex-situ molecular-beam-epitaxy (MBE) grown epitaxial Gd2O3 BOX layer. The x-ray diffraction analysis confirms the formation of twin-free epitaxial Ge layer in the case of in-situ sputtered Gd2O3 while twinned Ge layer is observed in the case of ex-situ MBE grown Gd2O3. The twinning of the Ge layer in the ex-situ process is further supported by transmission electron microscopy analysis. Finally, we have performed an experiment to study the impact of Gd2O3 BOX layer thickness on the crystal quality of Ge layer and show that the Ge layer crystal quality remains intact irrespective of BOX layer thickness. Therefore, we have achieved twin free Ge epitaxy in RF magnetron sputter system, equivalent to in-situ All-MBE SPE process. Such a process enables low-cost GeOI wafer manufacturing for cost-effective RF transistors.

Electrodeposition of crystalline silicon films from silicon dioxide for low-cost photovoltaic applications

Crystalline-silicon solar cells have dominated the photovoltaics market for the past several decades. One of the long standing challenges is the large contribution of silicon wafer cost to the overall module cost. Here, we demonstrate a simple process for making high-purity solar-grade silicon films directly from silicon dioxide via a one-step electrodeposition process in molten salt for possible photovoltaic applications. High-purity silicon films can be deposited with tunable film thickness and doping type by varying the electrodeposition conditions. These electrodeposited silicon films show about 40 to 50% of photocurrent density of a commercial silicon wafer by photoelectrochemical measurements and the highest power conversion efficiency is 3.1% as a solar cell. Compared to the conventional manufacturing process for solar grade silicon wafer production, this approach greatly reduces the capital cost and energy consumption, providing a promising strategy for low-cost silicon solar cells production.

Cost-Effective and Time-Efficient Failure Analysis Method for Yield Enhancement Utilizing Picked Sawn Wafer

Electrical and physical failure analyses have played a key role in the yield enhancement of large-scale integrated circuits. However, the growing cost of product wafers has progressively hindered their use for analysis, depending on the shrinkage of device dimensions. To overcome these difficulties, we propose a new analytical style that uses the remaining dies on a sawn wafer after all the good dies have been picked and taken for assembly. We call the resulting structure a “skeleton-wafer”. In the present study, we have developed a testing system that can handle a skeleton-wafer in the same manner as a conventional wafer. Basically, skeleton-wafer testing is performed at room temperature, given that commonly used dicing tapes have low heat-resistance. We have also developed a sophisticated method that enables analytical testing on the remaining dies at high temperature. A case example achieves high throughput and good contact characteristics, enabling the developed system to be of practical use in high-volume electrical failure analysis. We illustrate how our analytical testing system has improved cost-effectiveness and time-efficiency in yield enhancement activity.

3C-SiC/Si Heterostructure: An Excellent Platform for Position-Sensitive Detectors Based on Photovoltaic Effect.

Single-crystalline silicon carbide (3C-SiC) on the Si substrate has drawn significant attention in recent years due to its low wafer cost and excellent mechanical, chemical, and optoelectronic properties. However, the applications of the structure have primarily been focused on piezoresistive and pressure sensors, bio-microelectromechanical system, and photonics. Herein, we report another promising application of the heterostructure as a laser spot position-sensitive detector (PSD) based on the lateral photovoltaic effect (LPE) under nonuniform optical illuminations at zero-bias conditions. The LPE shows a linear dependence on spot positions, and the sensitivity is found to be as high as 33 mV/mm under an illumination of 2.8 W/cm2 (635 nm). The structure also exhibits a linear dependence of the LPE over a large distance (7 mm) between two electrodes, which is crucial for PSDs as the region with a linear dependence of LPE is only usable for PSDs. The LPE at different spot positions and under different illumination conditions have been investigated and explained based on the energy-band analysis. The temperature dependence of the LPE and position sensitivity is also investigated. Furthermore, the two-dimensional mapping of the lateral photovoltages reveals the potential for utilizing the 3C-SiC/Si heterostructure to detect the laser spot position precisely on a plane.

Passivation Studies on Single-Junction GaAs Thin Film Solar Cells on Flexible Metal Tapes for Low-Cost Photovoltaics

Despite the high efficiency of III–V solar cells based on gallium arsenide, their usage in large-scale terrestrial application is very limited due to the excessive cost of GaAs and Ge wafers. Herein, we have developed high-quality epitaxial semiconductor thin films on inexpensive flexible metal tapes to overcome the wafer cost as well as to benefit from the lower manufacturing cost of roll-to-roll processing. Metal organic chemical vapor deposition (MOCVD) is used to grow high-quality epitaxial GaAs solar cell structure on “single-crystalline-like” germanium film on epi-ready metal tape. These epitaxial GaAs films exhibit excellent crystalline alignment with high carrier mobility. The fabricated device is further processed for contact deposition via photolithography. Citric acid used for etching GaAs also resulted in effective passivation of the devices. Passivation of GaAs solar cells with various base thicknesses of 1140, 840, and 380 nm and various device sizes has been demonstrated. After passivation,...

Design and Measurement Requirements for Short Flow Test Arrays to Characterize Emerging Memories

Emerging non-volatile memories are becoming increasingly attractive for embedded and storage-class applications. Among the development challenges of Back-End integrated memory cells are long learning cycles and high wafer cost. We propose a short-flow based approach for characterization of Memory Arrays using a Cross-Point Array structure and highly parallel Parametric Test. A detailed analysis of design requirements and testability, including inverse circuit simulation, confirms feasibility of the approach to reduce Turn-Around Time and development costs.

Leakage Suppression Approaches in Bulk FinFETs

The Bulk FinFETs are preferred due to its low wafer cost, less defect density and less heat transfer even though the substrate leakage problem will turn up. Technological complexity and mobility degradations prevent the usage of substrate doping and variation in isolation oxide thickness to reduce off current. Stack gate technology bring down the leakage by using two gate materials with undoped substrate which is free from random dopant fluctuations. The corner effect of bulk FinFET is minimised by using corner implantation and an optimal design of FinFET is obtained. Structure with different high-k dielectric spacers is analysed to see the device performance on 3-D TCAD device simulator. It is observed that as the dielectric constant increases, performance also increases which is a requisite for low power application of the bulk FinFET.

An experimental study of optoelectronic properties of porous silicon for solar cell application

The main aim of this paper is to enhance the efficiency of solar cell by reducing the reflectivity with the cost effective approach. If resistivity of the silicon wafer is increased the wafer cost is decreased. Hence, the high resistive p-type silicon wafer is used here to fabricate the porous silicon. Electro chemical etching process is used to synthesize the porous silicon from the high resistive bulk silicon. The etching parameters like current density is maintained as constant as 10 mA/cm2 and etching time are varied as 60, 120 and 180 min. Electrochemical etchant like HF and isopropanol are mixed in the ratio of 1:2. The porosity is determined by gravimetric method and the photoluminescence and spectrum absorption are investigated by using the spectroflurometer. Based on the result, refractive index and band gap is determined. The obtained photoluminescence response shows that if the porosity of the Psi is increased, then the band gap is also increased. The maximum porosity achieved is 84.21% for the etching time 180 min. and maximum energy band gap is obtained as 1.8921 eV for the wavelength 655.35 nm. Hence, it is proved that low cost, high resistive wafer is also capable to fabricate the anti reflective solar cell.