Abstract
Emerging non-volatile memories are becoming increasingly attractive for embedded and storage-class applications. Among the development challenges of Back-End integrated memory cells are long learning cycles and high wafer cost. We propose a short-flow based approach for characterization of Memory Arrays using a Cross-Point Array structure and highly parallel Parametric Test. A detailed analysis of design requirements and testability, including inverse circuit simulation, confirms feasibility of the approach to reduce Turn-Around Time and development costs.
Highlights
The embedded non-volatile memory (NVM) market has traditionally been dominated by embedded Flash, based either on Floating Gate or Charge Trap SONOS technology
The IBL current measured at each of BL terminals is not just a function of the Von voltage and Cell resistance, but many other parameters. Another factor which needs considering for the selectorless cross-point array is a potential risks of voltage overshoot or current spike during the programming pulse, caused by fast resistance change from high-resistance state (HRS) → low-resistance state (LRS)
In the following analysis we focus on marginal bad bits either “stuck at HRS,” a bit that does not change its state in response to programming pulses while programming “1,” or “stuck at LRS,” a bit which does not change under conditions of programming “0.”
Summary
The embedded non-volatile memory (NVM) market has traditionally been dominated by embedded Flash, based either on Floating Gate or Charge Trap SONOS technology. We proposed such an approach to characterize memory elements using short flow test vehicle with cross-point arrays, as shown in Fig. 3 [8].
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