A testability analysis method for register-transfer level descriptions

Abstract

In this paper, we propose a new testability analysis method for Register-Transfer Level (RTL) descriptions. The proposed method is based on the idea of testability analysis in terms of data-flow and control structure which can be extracted from RTL designs. We analyze testability of RTL descriptions with more testability measures than those of conventional gate-level testability, so that the method provides information for design for testability (DFT). We have implemented the presented method and experimental results show that we can reduce circuit cost for test and achieve highly testable circuits by DFT using our RTL testability analysis.