Von Neumann Bottleneck Research Articles

Energy-efficient Mott activation neuron for full-hardware implementation of neural networks.

To circumvent the von Neumann bottleneck, substantial progress has been made towards in-memory computing with synaptic devices. However, compact nanodevices implementing non-linear activation functions are required for efficient full-hardware implementation of deep neural networks. Here, we present an energy-efficient and compact Mott activation neuron based on vanadium dioxide and its successful integration with a conductive bridge random access memory (CBRAM) crossbar array in hardware. The Mott activation neuron implements the rectified linear unit function in the analogue domain. The neuron devices consume substantially less energy and occupy two orders of magnitude smaller area than those of analogue complementary metal-oxide semiconductor implementations. The LeNet-5 network with Mott activation neurons achieves 98.38% accuracy on the MNIST dataset, close to the ideal software accuracy. We perform large-scale image edge detection using the Mott activation neurons integrated with a CBRAM crossbar array. Our findings provide a solution towards large-scale, highly parallel and energy-efficient in-memory computing systems for neural networks.

MXenes for memristive and tactile sensory systems

One of the most effective approaches to solving the current problem arising from the von Neumann bottleneck in this period of data proliferation is the development of intelligent devices that mimic the human learning process. Information sensing and processing/storage are considered to be the essential processes of learning. Therefore, high-performance sensors, memory/synaptic devices, and relevant intelligent artificial tactile perception systems are urgently needed. In this regard, innovative device concepts and emerging two-dimensional materials have recently received considerable attention. Herein, we discuss the development of MXenes for applications in tactile sensors, memristors, and artificial tactile perception systems. First, we summarize the structures, common properties, and synthesis and assembly techniques of MXenes. We then discuss the applications of MXenes in tactile sensors, memristors, and relevant neuromorphic-based artificial tactile perception systems along with the related working mechanisms. Finally, we present the challenges and prospects related to MXene synthesis, assembly, and application.

A Dual-Mode In-Memory Computing Unit Using Spin Hall-Assisted MRAM for Data-Intensive Applications

The emerging big data application poses many non-traditional challenges to a conventional computing system. The processing of a large amount of data in a conventional computing system involves frequent data movement between the processor and the memory. As a result, power consumption and latency of the system increases, most commonly known as the von Neumann bottleneck. To address this von Neumann bottleneck, processing in memory is considered one of the most promising solutions for energy-efficient computing in data-intensive applications. Therefore, in this work, we propose an in-memory computing unit based on emerging non-volatile magnetic random access memory (MRAM), which can perform computations directly within the memory. We call the proposed memory unit computational MRAM (C-MRAM). The proposed array works in two modes: 1) memory mode, where it acts as standard memory with the additional advantage of non-volatility, and 2) logic mode, where it performs the computation inside the memory array. To demonstrate the benefits of the proposed C-MRAM array, we realize an approximate adder (Ax-ADD) for energy-constraint applications in which further power saving is achieved by relaxing the demand for computational accuracy. Furthermore, we propose to use the C-MRAM array in hybrid multi-bank architecture, which offers the flexibility of reconfiguring the proposed C-MRAM as a memory array or logic array to meet the requirement of a wide range of applications. The simulation result shows that the proposed array can efficiently perform memory, logic, and arithmetic operation in 2, 4, and 6 ns while consuming 0.2, 0.47, and 0.7 pJ of energy.

Interface controlled thermal resistances\xa0of ultra-thin chalcogenide-based phase change memory devices

Phase change memory (PCM) is a rapidly growing technology that not only offers advancements in storage-class memories but also enables in-memory data processing to overcome the von Neumann bottleneck. In PCMs, data storage is driven by thermal excitation. However, there is limited research regarding PCM thermal properties at length scales close to the memory cell dimensions. Our work presents a new paradigm to manage thermal transport in memory cells by manipulating the interfacial thermal resistance between the phase change unit and the electrodes without incorporating additional insulating layers. Experimental measurements show a substantial change in interfacial thermal resistance as GST transitions from cubic to hexagonal crystal structure, resulting in a factor of 4 reduction in the effective thermal conductivity. Simulations reveal that interfacial resistance between PCM and its adjacent layer can reduce the reset current for 20 and 120 nm diameter devices by up to ~ 40% and ~ 50%, respectively. These thermal insights present a new opportunity to reduce power and operating currents in PCMs.

Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores

Single-issue processor cores are very energy efficient but suffer from the von Neumann bottleneck, in that they must explicitly fetch and issue the loads/storse necessary to feed their ALU/FPU. Each instruction spent on moving data is a cycle not spent on computation, limiting ALU/FPU utilization to 33 percent on reductions. We propose “Stream Semantic Registers” to boost utilization and increase energy efficiency. SSR is a lightweight, non-invasive RISC-V ISA extension which implicitly encodes memory accesses as register reads/writes, eliminating a large number of loads/stores. We implement the proposed extension in the RTL of an existing multi-core cluster and synthesize the design for a modern 22 nm technology. Our extension provides a significant, 2x to 5x, architectural speedup across different kernels at a small 11 percent increase in core area. Sequential code runs 3x faster on a single core, and 3x fewer cores are needed in a cluster to achieve the same performance. The utilization increase to almost 100 percent in leads to a 2x energy efficiency improvement in a multi-core cluster. The extension reduces instruction fetches by up to 3.5x and instruction cache power consumption by up to 5.6x. Compilers can automatically map loop nests to SSRs, making the changes transparent to the programmer.

Efficient Parallel Multi‐Bit Logic‐in‐Memory Based on a Ultrafast Ferroelectric Tunnel Junction Memristor

AbstractMemristive logic‐in‐memory (LIM) is an attractive candidate for in‐memory computing and thus would overcome some of the issues concerning the von Neumann bottleneck, which has been intensively investigated. Here, a multi‐bit and functionally complete LIM strategy is designed to efficiently perform multi logical functions in parallel. This strategy is experimentally demonstrated by a multi‐bit ferroelectric tunnel junction (FTJ) memristor with a sub‐nanosecond operation speed which is nearly two orders of magnitude faster than the previous memristive LIM. Using the four resistance states (2‐bit) of only a single FTJ memristor cell, two logical computations are successfully performed in parallel, and the 16 complete Boolean logic functions are implemented within only two steps. In addition, the multi‐encoding schemes are proposed to further improve the efficiency and flexibility of parallel logical computations. Accordingly, the 1‐bit binary full adder can be implemented using as less as three parallel memristors by only performing five steps, and on this basis the N‐bit full adder can also be realized. These results provide a highly efficient LIM approach, which could be a promising candidate for future computing architecture.

Graphene oxide based synaptic memristor device for neuromorphic computing

Brain-inspired neuromorphic computing which consist neurons and synapses, with an ability to perform complex information processing has unfolded a new paradigm of computing to overcome the von Neumann bottleneck. Electronic synaptic memristor devices which can compete with the biological synapses are indeed significant for neuromorphic computing. In this work, we demonstrate our efforts to develop and realize the graphene oxide (GO) based memristor device as a synaptic device, which mimic as a biological synapse. Indeed, this device exhibits the essential synaptic learning behavior including analog memory characteristics, potentiation and depression. Furthermore, spike-timing-dependent-plasticity learning rule is mimicked by engineering the pre- and post-synaptic spikes. In addition, non-volatile properties such as endurance, retentivity, multilevel switching of the device are explored. These results suggest that Ag/GO/fluorine-doped tin oxide memristor device would indeed be a potential candidate for future neuromorphic computing applications.

Electrolyte-gated transistors for neuromorphic applications

Von Neumann computers are currently failing to follow Moore’s law and are limited by the von Neumann bottleneck. To enhance computing performance, neuromorphic computing systems that can simulate the function of the human brain are being developed. Artificial synapses are essential electronic devices for neuromorphic architectures, which have the ability to perform signal processing and storage between neighboring artificial neurons. In recent years, electrolyte-gated transistors (EGTs) have been seen as promising devices in imitating synaptic dynamic plasticity and neuromorphic applications. Among the various electronic devices, EGT-based artificial synapses offer the benefits of good stability, ultra-high linearity and repeated cyclic symmetry, and can be constructed from a variety of materials. They also spatially separate “read” and “write” operations. In this article, we provide a review of the recent progress and major trends in the field of electrolyte-gated transistors for neuromorphic applications. We introduce the operation mechanisms of electric-double-layer and the structure of EGT-based artificial synapses. Then, we review different types of channels and electrolyte materials for EGT-based artificial synapses. Finally, we review the potential applications in biological functions.

A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications

Resistive random access memory (ReRAM)-based computing in-memory (CIM) is a promising solution to overcome the von-Neumann bottleneck in conventional computing architectures. We propose a reconfigurable ReRAM architecture using a novel 4T2R bit-cell that supports non-volatile storage and two types of CIM operations: i) ternary content addressable memory (TCAM) and ii) in-memory dot product (IM-DP) for neural networks. The proposed 4T2R cell occupies a smaller area than prior SRAM-based CIM bit-cells. A $128\times128$ ReRAM macro is designed in 40nm CMOS technology. For TCAM operations, it allows a search word-length of 128 bits. For IM-DP operations, it can compute parallel dot products using binary inputs and ternary weights. The simulated search delay for TCAM operation is 0.92 ns at VDD = 0.9 V and the simulated energy efficiency for IM-DP operation is 223.6 TOPS/W at VDD = 0.7 V. Monte-Carlo simulations show a standard deviation of 4.9% in accumulate operation for IM-DP which corresponds to a classification accuracy of 95.7% on the MNIST dataset and 81.7% on the CIFAR-10 dataset.

Electrically Reconfigurable 3D Spin‐Orbitronics

AbstractThe explosive demands of storage capacity and the von Neumann bottleneck of modern computer architectures trigger many innovations in information technology. Amongst them, nonvolatile spintronics attract considerable attentions for which can embed the computation capability into memory, enable neuromorphic, and probabilistic computing. These exciting progresses typically rely on the manipulation of the relative magnetization orientations of two magnetic layers. By extending to 3D spintronic architectures made of multiple magnetic layers (n), the exponentially increased 2n magnetic states can provide ample opportunities for implementing novel spintronic functionalities. Here, through building perpendicularly magnetized 3D spin‐orbitronic architectures – [Pt/Fe1−xTbx/Si3N4]n multilayers, it is demonstrated the electrical programing of 2n memory states via current‐induced spin–orbit torques (SOTs), and the accompanied reconfigurable multifunction in‐memory logic features in a single four‐terminal Hall device. Further, an electrical readout of these 2n states, together with the implementation of Boolean logic gates and digital circuitry such as 2–4 and 3–8 decoders, are successfully conducted. More complex logic circuits are also envisioned. The experiments thus substantiate 3D spin‐orbitronic structures as a promising platform for exponentially boosting the storage capacity and accommodating in‐memory computing that can be important for promoting the emerging 3D nanospintronics.

Competing memristors for brain-inspired computing.

SummaryThe expeditious development of information technology has led to the rise of artificial intelligence (AI). However, conventional computing systems are prone to volatility, high power consumption, and even delay between the processor and memory, which is referred to as the von Neumann bottleneck, in implementing AI. To address these issues, memristor-based neuromorphic computing systems inspired by the human brain have been proposed. A memristor can store numerous values by changing its resistance and emulate artificial synapses in brain-inspired computing. Here, we introduce six types of memristors classified according to their operation mechanisms: ionic migration, phase change, spin, ferroelectricity, intercalation, and ionic gating. We review how memristor-based neuromorphic computing can learn, infer, and even create, using various artificial neural networks. Finally, the challenges and perspectives in the competing memristor technology for neuromorphic computing systems are discussed.

Implementation of synaptic learning rules by TaO x memristors embedded with silver nanoparticles* *Project supported by the National Natural Science Foundation of China (Grant No. 61674038), the Natural Science Foundation of Fujian Province, China (Grant No. 2019J01218), the Fund from the Fujian Science and Technology Innovation Laboratory for Optoelectronic Information of China (Grant No. 2021ZR145), and the Science Fund from

As an alternative device for neuromorphic computing to conquer von Neumann bottleneck, the memristor serving as an artificial synapse has attracted much attention. The TaO x memristors embedded with silver nanoparticles (Ag NPs) have been fabricated to implement synaptic plasticity and to investigate the effects of Ag NPs. The TaO x memristors with and without Ag NPs are capable of simulating synaptic plasticity (PTP, STDP, and STP to LTP), learning, and memory behaviors. The conduction of the high resistance state (HRS) is driven by Schottky-emission mechanism. The embedment of Ag NPs causes the low resistance state (LRS) conduction governed by a Poole–Frenkel emission mechanism instead of a space-charge-limited conduction (SCLC) in a pure TaO x system, which is ascribed to the Ag NPs enhancing electric field to produce additional traps and to reduce Coulomb potential energy of bound electrons to assist electron transport. Consequently, the enhanced electric fields induced by Ag NPs increase the learning strength and learning speed of the synapses. Additionally, they also improve synaptic sensitivity to stimuli. The linearity of conductance modulation and the reproducibility of conductance are improved as well.

Recent Progress of Protein‐Based Data Storage and Neuromorphic Devices

By virtue of energy efficiency, high speed, and parallelism, brain‐inspired neuromorphic computing is a promising technology to overcome the von Neumann bottleneck and capable of processing massive sophisticated tasks in the background of big data. The abilities of perceiving and reacting to events in artificial neuromorphic systems allow us to build the communicative electronic–biological interfaces to get closer to electronic life. Protein materials offer great application potentials in such a system due to their sustainability, low cost, controllable hierarchical structure, intrinsic biocompatibility, and biodegradability. Herein, a timely review of the development of protein‐based memories for data storage and neuromorphic computing is provided. Proteins’ unique mechanical, electronic, optical properties, and their broad applications are discussed. Then, the progress of protein‐based two‐terminal memristor and three‐terminal transistor‐type memory is reviewed, and their applications for data storage, logic circuit, and neuromorphic computing are introduced. Finally, the major challenges and outlook toward the future developing directions of protein‐based computing systems are pointed out.

Neuromorphic Engineering: From Biological to Spike-Based Hardware Nervous Systems.

The human brain is a sophisticated, high-performance biocomputer that processes multiple complex tasks in parallel with high efficiency and remarkably low power consumption. Scientists have long been pursuing an artificial intelligence (AI) that can rival the human brain. Spiking neural networks based on neuromorphic computing platforms simulate the architecture and information processing of the intelligent brain, providing new insights for building AIs. The rapid development of materials engineering, device physics, chip integration, and neuroscience has led to exciting progress in neuromorphic computing with the goal of overcoming the von Neumann bottleneck. Herein, fundamental knowledge related to the structures and working principles of neurons and synapses of the biological nervous system is reviewed. An overview is then provided on the development of neuromorphic hardware systems, from artificial synapses and neurons to spike-based neuromorphic computing platforms. It is hoped that this review will shed new light on the evolution of brain-like computing.

Optoelectronic Synaptic Devices for Neuromorphic Computing

Neuromorphic computing can potentially solve the von Neumann bottleneck of current mainstream computing because it excels at self‐adaptive learning and highly parallel computing and consumes much less energy. Synaptic devices that mimic biological synapses are critical building blocks for neuromorphic computing. Inspired by recent progress in optogenetics and visual sensing, light has been increasingly incorporated into synaptic devices. This paves the way to optoelectronic synaptic devices with a series of advantages such as wide bandwidth, negligible resistance–capacitance (RC) delay and power loss, and global regulation of multiple synaptic devices. Herein, the basic functionalities of synaptic devices are introduced. All kinds of optoelectronic synaptic devices are then discussed by categorizing them into optically stimulated synaptic devices, optically assisted synaptic devices, and synaptic devices with optical output. Existing practical scenarios for the application of optoelectronic synaptic devices are also presented. Finally, perspectives on the development of optoelectronic synaptic devices in the future are outlined.

Growing Perovskite Quantum Dots on Carbon Nanotubes for Neuromorphic Optoelectronic Computing

AbstractBrain‐inspired (neuromorphic) computing that offers lower energy consumption and parallelism (simultaneous processing and memorizing) compared to von Neumann computing provides excellent opportunities in many computational tasks ranging from image recognition to speech processing. To accomplish neuromorphic computing, highly efficient optoelectronic synapses, which can be the building blocks of optoelectronic neuromorphic computers, are necessary. Currently, carbon nanotubes (CNTs), an attractive candidate to develop circuit‐level photonic synapses, provide weak light responses. The inferior photoresponse of CNTs increases the energy consumption of neuromorphic optoelectronic devices. Herein, a method to grow organic–inorganic halide perovskite quantum dots (PQDs) directly on multiwall CNTs (MWCNTs) to increase the photosensitivity of optoelectronic synapses is demonstrated. The new hybrid material synchronizes the high photoresponse of PQDs and the excellent electrical properties of MWCNTs to provide photonic memory under very low light intensity (125 µW cm−2). However, neat MWCNTs do not show any detectable light response at the tested light intensity, as high as 25 mW cm−2. Since the PQDs are grown directly on and in the MWCNTs, the hybrid PQD‐MWCNT provides a new direction for the future MWCNT‐based optoelectronic devices for neuromorphic computing with a potential to break the von Neumann bottleneck.

Ultrahigh-Density 3-D Vertical RRAM With Stacked Junctionless Nanowires for In-Memory-Computing Applications

The Von-Neumann bottleneck is a clear limitation for data-intensive applications, bringing in-memory computing (IMC) solutions to the fore. Since large data sets are usually stored in nonvolatile memory (NVM), various solutions have been proposed based on emerging memories, such as OxRAM, that rely mainly on area hungry, one transistor (1T) one OxRAM (1R) bit-cell. To tackle this area issue, while keeping the programming control provided by 1T1R bit-cell, we propose to combine gate-all-around stacked junctionless nanowires (1JL) and OxRAM (1R) technology to create a 3-D memory pillar with ultrahigh density. Nanowire junctionless transistors have been fabricated, characterized, and simulated to define current conditions for the whole pillar. Finally, based on Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, we demonstrated successfully scouting logic operations up to three-pillar layers, with one operand per layer.

Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

As we approach the end of Moore’s law, many alternative devices are being explored to satisfy the performance requirements of modern integrated circuits. At the same time, the movement of data between processing and memory units in contemporary computing systems (‘von Neumann bottleneck’ or ‘memory wall’) necessitates a paradigm shift in the way data is processed. Emerging resistance switching memories (memristors) show promising signs to overcome the ‘memory wall’ by enabling computation in the memory array. Majority logic is a type of Boolean logic which has been found to be an efficient logic primitive due to its expressive power. In this review, the efficiency of majority logic is analyzed from the perspective of in-memory computing. Recently reported methods to implement majority gate in Resistive RAM array are reviewed and compared. Conventional CMOS implementation accommodated heterogeneity of logic gates (NAND, NOR, XOR) while in-memory implementation usually accommodates homogeneity of gates (only IMPLY or only NAND or only MAJORITY). In view of this, memristive logic families which can implement MAJORITY gate and NOT (to make it functionally complete) are to be favored for in-memory computing. One-bit full adders implemented in memory array using different logic primitives are compared and the efficiency of majority-based implementation is underscored. To investigate if the efficiency of majority-based implementation extends to n-bit adders, eight-bit adders implemented in memory array using different logic primitives are compared. Parallel-prefix adders implemented in majority logic can reduce latency of in-memory adders by 50–70% when compared to IMPLY, NAND, NOR and other similar logic primitives.

Memristive Devices from CuO Nanoparticles.

Memristive systems can provide a novel strategy to conquer the von Neumann bottleneck by evaluating information where data are located in situ. To meet the rising of artificial neural network (ANN) demand, the implementation of memristor arrays capable of performing matrix multiplication requires highly reproducible devices with low variability and high reliability. Hence, we present an Ag/CuO/SiO2/p-Si heterostructure device that exhibits both resistive switching (RS) and negative differential resistance (NDR). The memristor device was fabricated on p-Si and Indium Tin Oxide (ITO) substrates via cost-effective ultra-spray pyrolysis (USP) method. The quality of CuO nanoparticles was recognized by studying Raman spectroscopy. The topology information was obtained by scanning electron microscopy. The resistive switching and negative differential resistance were measured from current–voltage characteristics. The results were then compared with the Ag/CuO/ITO device to understand the role of native oxide. The interface barrier and traps associated with the defects in the native silicon oxide limited the current in the negative cycle. The barrier confined the filament rupture and reduced the reset variability. Reset was primarily influenced by the filament rupture and detrapping in the native oxide that facilitated smooth reset and NDR in the device. The resistive switching originated from traps in the localized states of amorphous CuO. The set process was mainly dominated by the trap-controlled space-charge-limited; this led to a transition into a Poole–Frenkel conduction. This research opens up new possibilities to improve the switching parameters and promote the application of RS along with NDR.

STAR: Synthesis of Stateful Logic in RRAM Targeting High Area Utilization

Processing-in-memory (PIM) exploits massive parallelism with high energy efficiency and becomes a promising solution to the von Neumann bottleneck. Recently, the emerging metal-oxide resistive random access memory (RRAM) shows its potential to construct a PIM architecture, because several stateful logic operations, e.g., IMP and NOR, can be executed in an RRAM crossbar in parallel. Previous synthesis flows focus on improving latency with stateful logic operations, but they ignore that the memory should be used primarily for storage. i.e., most of the area in the crossbar is used for computation but not storage. In this situation, storage and computation still have to be separated into different crossbars, which leads to considerable data transfer overhead and limited parallelism. In this work, we define the ratio of storage in a crossbar as area utilization. We aim to improve the area utilization without throughput loss by proposing STAR, a novel synthesis flow for the stateful logic. We present two optimization strategies to reduce the computation area in STAR. First, we reduce the area for redundant inputs. For the shared constants among different rows (or columns), we encode them as immediate values into the control signals without writing them into the crossbar at runtime. For the other inputs, we only store one copy of them in the crossbar. Second, we reduce the area for intermediate variables by reusing invalid cells. And we design a scheduling algorithm to find a computation sequence with the minimal variable erasing cycles. Invalid primary inputs can also be erased in this algorithm. Furthermore, we present a case study of the image convolution to demonstrate the effectiveness of STAR. Experimental evaluation shows that STAR achieves 33.03% more area utilization and a 1.43x throughput compared to SIMPLER, the state-of-the-art stateful logic synthesis flow. Our image convolution implementation also provides 78.36% more area utilization and a 1.48x throughput compared with IMAGING, the state-of-the-art stateful logic-based image processing accelerator.