Voltage Transistors Research Articles

DC characteristics of a dynamic vision sensor's photoreceptor circuit evaluated for event-based sensing in the mid-wave infrared

Forthcoming infrared event-based sensors will have utility in the space-based surveillance domain where they could potentially perform traditional sensing and tracking functions with significantly enhanced temporal resolution and reduced downstream datalink demands and power consumption. As a first step toward extending event-based sensing technology into the mid-wave infrared, a DC simulation of the conventional event-based sensor unit cell's photoreceptor circuit is performed, and the results are compared with measurements of a printed circuit board implementation of the same circuit to assess what design freedom is available to interface the photoreceptor with a mid-wave infrared photodetector. Detailed analysis of the circuit and measurements provides insight into which fundamental properties of the transistors drive the photoreceptor's dynamic range and demonstrates several characteristics that are relevant to mid-wave infrared sensing. These characteristics include the capability to produce a stable, low voltage bias on the infrared photodetector to maximize sensitivity, and that operating the circuit below room temperature increases the photoreceptor's dynamic range. Measurements show that even the simplest implementation of the photoreceptor circuit exhibits a dynamic range of logarithmic compression of 150 dB at room temperature. However, the dynamic range is ultimately limited by the mid-wave infrared photodetector's dark current activation energy, which is significantly lower than the threshold voltage (energy) of the photoreceptor's feedback transistor and, thus, there is an incentive for the photodetector's dark current to be diffusion-limited.

Arbitrary Waveform Voltage Measuring Converter for Wideband AC Voltmeter

Alternating current (AС) voltage measurement is one of the most common types of measurements in various fields of science and technology. To evaluate the AC voltage level, special voltmeters are used which allow recording of amplitude, average and/or root mean square (RMS) voltage values. Among these measuring instruments, voltmeters of mean square voltage are especially significant because RMS is a fundamental physical characteristic of an electrical signal and is a true measure of power. The wide distribution of non-sinusoidal signals necessitates the creation of voltmeters for direct measurement of RMS. The main component of such voltmeter is an AC voltage to direct current (DC) voltage measuring converter based on the root-mean-square value level (AC RMS-DC converter). An analysis of existing technical solutions shows that it is advisable to use a thermoelectric converter (TEC) for high-precision measurement of RMS voltage of an arbitrary shape with a spectrum in the frequency band from 20 Hz to 20–50 MHz. Such a AC RMS-DC converter must contain a differential semiconductor TEC and an input broadband voltage amplifier with low nonlinearity of the frequency response. The aim of the paper was to develop a measuring AC RMS-DC converter of arbitrary shape voltage in which special attention is paid to modernization of the TEC and reduction of the AC RMS-DC converter error using corection of the frequency response of the input amplifier and introduction automatic calibration of the output voltage. Features of semiconductor chips and design of TEC in the form of a microcircuit or microassembly, results of converter’s and TEC elements’ parameters measurements are presented. A significant influence of the frequency response of the input amplifier and the offset voltage of the TEC transistors on the AC RMS-DC converter error was noted. Modernization of the input amplifier and introduction of automatic calibration of the output voltage ensured an error in a sinusoidal signal converting of less than 1 % in the range from 20 Hz to 50 MHz.

A comprehensive investigation of total ionizing dose effects on bulk FinFETs through TCAD simulation

This study investigates the total-ionizing-dose (TID) effect on bulk FinFETs under ON-state irradiation bias, aiming to analyze the cause and physical mechanism of irradiation enhancement effects. Utilizing technology computer-aided design (TCAD), for the first time, we find that parasitic transistors located at the apex of the shallow trench isolation (STI) oxide significantly contribute to the subthreshold degradation of the device, leading to a notable increase in off-state leakage current. Furthermore, under identical irradiation bias conditions, narrower-fin and shorter-channel devices exhibit a more pronounced increase in off-state leakage current. This escalation is attributed to an increased amount of trapped charge in the STI oxide and the elevated electrostatic potential of the punch-through stop (PTS) layer, respectively. Additionally, higher drain voltage reduces the threshold voltage of the STI parasitic transistors, resulting in an increased off-state current as drain voltage rises. In summary, investigating the TID effect of bulk FinFETs under ON-bias is crucial, as it can provide theoretical support for reinforcing nanostructured devices against irradiation-induced degradation.

Analysis and design of voltage-source parallel resonant class [formula omitted] inverter

In this paper, a detailed mathematical analysis process of the voltage-source parallel resonant (VSPR) class E/F3 inverter at 50% duty ratio is proposed. Combining the advantages of VSPR class E and F inverters, the performance of the proposed inverter can be improved greatly compared to the traditional. The transistor in the VSPR class E/F3 inverter is satisfied with zero-voltage switching(ZVS) and zero-voltage derivative switching(ZVDS) conditions. Moreover, two design freedoms can be obtained and the proposed analysis process is based on them, which can provide more flexible selections. Finally, a VSPR class E/F3 inverter is fabricated and the experiment is carried out. The measured normalized peak transistor voltage decreases by 25.6%. The output power reaches 5.06 W, and the efficiency reaches 93.75%. The measured results are well agreed with the theoretical and simulated.

Quantum coupling and self-heating impacts on threshold voltages of GaN metal–insulator-semiconductor high-electron-mobility transistors

A transient heat conduction equation has been proposed to describe the cooling process of a hot two-dimensional electron gas layer in a GaN-based transistor. This equation serves as the basis for a physical analytical model that explains the impacts of hot electrons in the hot two-dimensional electron gas layer via quantum coupling on the threshold voltage of GaN-based transistors. The temperature of the two-dimensional electron gas layer decreases to ambient temperature as time increases, and the threshold voltage shifts caused by such a temperature will recover with time. The proposed model accurately reflects the observed recovery of threshold voltage over time in experiments. At the same time, it offers insight into how the gate voltage, the source-drain voltage, and the ambient temperature can shift the threshold voltage in these transistors. The simplicity and analytic nature of this proposed model not only provide a physical origin of the threshold voltage instability in GaN-based devices but also offer the possibility for improving device reliability by selecting appropriate device physical parameters.

A gas sensing neural circuit for an olfactory neuron

A gas sensor can convert external gas concentration or species into electric voltage or current signals by physical adsorption or chemical changes. As a result, a gas sensor in a nonlinear circuit can be used as a sensitive sensor for detecting external gas signals from the olfactory system. In this paper, a gas sensor and a field-effect transistor are incorporated into a simple FithzHugh–Nagumo neural circuit for capturing and encoding external gas signals. An improved functional neural circuit is obtained, and the effect of gas concentration, gas species and neuronal activity can be discerned as the gate voltage, threshold voltage and activation coefficient of the field-effect transistor, respectively. The gas concentration can affect the neural activities from quiescent to normal working and, finally, to saturation state in bursting, spiking, periodic and chaotic firings with different frequencies. The effects of gas species and neuronal activity on the firing state can also be achieved in this functional neural circuit. In addition, variations in the gate voltage, threshold voltage and activation coefficient can cause switching between different firing modes. These results can be helpful in designing artificial olfactory devices for bionic gas recognition and other coupled systems arising in applied sciences.

A 40 mV cold-start circuit with bootstrap clock booster for thermoelectric energy harvesting

In this paper, a cold-start circuit with bootstrap clock booster for thermoelectric energy harvesting is proposed. The relationship between enhancing the clock swing amplitude and lowering the input voltage for a cross-coupled charge pump (CCCP) is analyzed. Based on the existing one-shot start-up mechanism, a series-parallel bootstrap clock booster (SP-BCB) for boosting the clock amplitude is proposed to lower the cold start voltage. Besides, a dynamic threshold MOS (DTMOS) technique for dynamically changing the threshold voltage of MOS transistors is used to achieve better conduction and leakage current suppression. The complete circuit is simulated in a 0.18-μm CMOS process. The simulated results demonstrate that using DTMOS technique and enhancing the clock swing amplitude can contribute to lowering the input voltage. The SP-BCB-based CCCP can boost the input voltage from 40 mV to 668 mV for a 500 MΩ load in 100 m s, which meets the requirement for one-shot start-up mechanism, realizing 40-mV integrated cold start for thermoelectric energy harvesting (TEH).

Novel clamping modulation for three‐phase buck‐boost ac choppers

AbstractThree‐phase ac choppers feature output voltage amplitude controllability and enable more compact system realizations compared to autotransformers. For the practical realization advantageously standard power transistor with unipolar voltage blocking capability such as MOSFETs can be employed as a naturally resulting offset voltage between the grid and the input‐stage starpoint ensures purely positive power transistor voltages. This offset voltage is, however, not strictly defined and may drift to higher voltage values, resulting in high power transistor voltage stresses and finally a potential overvoltage breakdown. Traditionally, the offset voltage drift is prevented by introducing discharge resistors across the input‐stage capacitors which, however, results in substantial ohmic losses. This paper analyzes the offset voltage formation in ac choppers and proposes a novel clamping modulation scheme which ensures a strictly defined and minimum time‐varying offset voltage without need for discharge resistors. Theoretical analyses and circuit simulations are finally experimentally verified with a 400 V (rms, line‐to‐line) 50 Hz grid connected three‐phase buck‐boost ac chopper with 3 kW rated power.

Tuning the Threshold Voltage of an Oxide Thin-Film Transistor by Electron Injection Control Using a p-n Semiconductor Heterojunction Structure.

Herein, a heterojunction structure integrating p-type tellurium (Te) and n-type aluminum-doped indium-zinc-tin oxide (Al:IZTO) is shown to precisely modulate the threshold voltage (VT) of the oxide thin-film transistor (TFT). The proposed architecture integrates Te as an electron-blocking layer and Al:IZTO as a charge-carrier transporting layer, thereby enabling controlled electron injection. The effects of incorporating the Te layer onto Al:IZTO are investigated, with a focus on X-ray photoelectron spectroscopy (XPS) analysis, in order to explain the behavior of oxygen vacancies and to depict the energy band structure configurations. By modulating the thickness and employing both single and double deposition methods for the heterojunction Te layer, a remarkable VT shift of up to +20 V is achieved. Furthermore, this study also shows excellent stability to a positive bias stress of +2 MV/cm for 10,000 s without additional passivation layers, demonstrating the robustness of the designed TFT. By a thorough optimization of the Al:IZTO/Te interface, the results demonstrate not only the substantial impact of the introduced heterojunction structure on VT control but also the endurance, durability, and stability of the optimized TFTs under prolonged long-term operating stress, thus offering promising prospects for tailored semiconductor device applications.

A Degradable Tribotronic Transistor for Self-Destructing Intelligent Package e-Labels.

Recently, discarded electronic products have caused serious environmental pollution and information security issues, which have attracted widespread attention. Here, a degradable tribotronic transistor (DTT) for self-destructing intelligent package e-labels has been developed, integrated by a triboelectric nanogenerator and a protonic field-effect transistor with sodium alginate as a dielectric layer. The triboelectric potential generated by external contact electrification is used as the gate voltage of the organic field-effect transistor, which regulates carrier transport through proton migration/accumulation. The DTT has successfully demonstrated its output characteristics with a high sensitivity of 0.336 mm-1 and a resolution of over 100 μm. Moreover, the DTT can be dissolved in water within 3 min and completely degraded in soil within 12 days, demonstrating its excellent degradation characteristics, which may contribute to environmental protection. Finally, an intelligent package e-label based on the modulation of the DTT is demonstrated, which can display information about the package by a human touch. The e-label will automatically fail due to the degradation of the DTT over time, achieving the purpose of information confidentiality. This work has not only presented a degradable tribotronic transistor for package e-labels but also exhibited bright prospects in military security, information hiding, logistics privacy, and personal affairs.

Insights into Sub‐Thermionic Transport in Schottky Barrier FETs

AbstractBoltzmann carrier statistics restrict the sub‐threshold swing (SS ≥ 60 mVdec–1) and, consequently, the supply voltage (≈ 1 V) of the thermionic transistor. This primary bottleneck results in rapidly increasing power consumption, heating, and associated reliability/scalability challenges as more devices are packed into a small footprint. Despite significant efforts from the device community, a suitable sub‐thermionic alternative is yet to emerge. In this work, an attempt is made to understand the physics of Schottky barrier FETs demonstrating SS < 60 mVdec–1, as evident in some experimental results. Employing the in‐house TCAD tool, the electrostatic potential in the device is accurately modeled with the sweeping gate bias. Next, the Tsu–Esaki model is used to compute the tunneling current. The analysis shows that the steep SS results from an abrupt change in the tunneling barrier profile, from a step‐like to a triangular‐like. However, in the ON regime, the drift component begins to dominate the transfer characteristics. Thus, the subtle interplay between the drift and tunneling components of transport leads to SS < 60 mVdec–1 in OFF‐state with improved in ON‐state. Finally, using the calibrated model, the performance metrics of an all‐2D material‐based CMOS inverter operating at a low VDD ≈ 0.6 V are projected.

The Enhanced Performance of Oxide Thin-Film Transistors Fabricated by a Two-Step Deposition Pressure Process.

It is usually difficult to realize high mobility together with a low threshold voltage and good stability for amorphous oxide thin-film transistors (TFTs). In addition, a low fabrication temperature is preferred in terms of enhancing compatibility with the back end of line of the device. In this study, α-IGZO TFTs were prepared by high-power impulse magnetron sputtering (HiPIMS) at room temperature. The channel was prepared under a two-step deposition pressure process to modulate its electrical properties. X-ray photoelectron spectra revealed that the front-channel has a lower Ga content and a higher oxygen vacancy concentration than the back-channel. This process has the advantage of balancing high mobility and a low threshold voltage of the TFT when compared with a conventional homogeneous channel. It also has a simpler fabrication process than that of a dual active layer comprising heterogeneous materials. The HiPIMS process has the advantage of being a low temperature process for oxide TFTs.

Low voltage driven P3HT/PS phototransistor for ultra-high power efficiency UV sensing

This study explores the physical properties and electrical characteristics of a regioregular poly 3-hexylthiophene (rr-P3HT) semiconductor blended with the polymer insulator polystyrene. Given the high operating voltage required by conventional P3HT transistors, we employed a hybrid dielectric layer, combining plasma-reacted metal oxide with a polymer pre-layer (AlOx/PMMA and HfOx/PMMA), to reduce the operating voltage of P3HT transistors. As a result, an operating voltage lower than −5 V for the blended sample was achieved. The structural, morphological, and electrical properties of the prepared blended sample were investigated using XRD, AFM, XPS, UV–Visible spectroscopy, Raman spectroscopy, and I–V characteristics. The blended sample exhibits improved crystalline ordering and an extended effective conjugation length, accompanied by an increased formation of dendritic P3HT fibrils that enhance UV absorption. PS captures generated electrons, effectively delaying their recombination with generated holes in P3HT. This leads to heightened UV responsivity in P3HT/PS transistors. The key discovery of this study is the ultra-low power consumption UV sensing device. The blended sample, illuminated with a UV intensity of 550 μW/cm2, exhibited the highest sensitivity of 194.5, nearly 60 times higher than that of pristine P3HT. Consequently, our investigated device shows promise for applications in visible-blind sunlight or environmental monitoring systems, given its ultra-high-power efficiency.

Analysis and design of voltage‐source parallel resonant class E frequency multiplier

AbstractIn this paper, the analysis and design process of the voltage‐source parallel resonant class E frequency multiplier with a 50% duty ratio is proposed. The proposed circuit adopts two series resonant filters for reducing the interference of harmonics to the output waveform and achieves zero‐voltage switching (ZVS) and zero‐voltage derivation switching (ZVDS) conditions. The design equations for the proposed circuit are given in detail. The new type class E frequency multiplier can operate at lower transistor voltage stress, higher operating frequency, and larger output power. Meanwhile, the volume and weight of the measured circuit are greatly decreased compared to the conventional class E frequency multiplier. To demonstrate the analysis process, the circuit operating at 1 MHz is fabricated and measured. Compared to the traditional class E frequency multiplier, the transistor peak voltage is reduced by 47.9%, the diameter of the resonant inductor core is decreased by 56.2%, and the measured efficiency can reach 95.1%. The theoretical and simulated results are all agreed with the experimental results.

Ultra-low-power CMOS ring oscillator with minimum power consumption of 2.9 pW using low-voltage biasing technique

Abstract The need for low-power low-voltage circuit so lutions increases significantly with the rapid spread of wireless sensor network (WSN) and energy harvesting applications. The design of Complementary Metal-Oxide Semiconductor (CMOS) oscillators in sub-threshold region is challenged by the limits of the minimum start-up sup ply voltage, the power available from the harvester, die area, the demand of fully integrated CMOS circuits, and the additional auxiliary circuits that are needed to stabilize the frequency vs a supply voltage V DD. In this work, low-power CMOS oscillator with a simplified design is proposed in order to overcome the aforementioned obstacles. The circuit is designed using 2.5 µm 2-polySi 2-metal CMOS technology from IMB–CNM (CSIC) [1] with a threshold voltage of n-channel metal oxide semiconductor NMOS and p-channel metal oxide semiconductor PMOS transistors of 0.86 and −1.52 V, respectively. The suggested oscillator is capable to start up even in the deep sub-threshold region at V DD of 0.25 V. Accordingly, the minimum power consumption is 2.9 pW with an oscillation frequency of 2 Hz. The circuit can produce a P–P voltage of the oscillation signal equal to the supply voltage within a power supply range of 0.25–1.25 V.

A wide locking range injection‐locked frequency divider with an auto‐adjusted injection bias

AbstractThis paper presents a Ku‐band divide‐by‐2 direct injection‐locked frequency divider (ILFD) with a wide locking range (LR) and high input sensitivity. The proposed ILFD incorporates an auto‐adjusted injection bias that uses a power detector (PD) to convert the power of the injected signal to a DC voltage. The bias voltage of the injection transistor is then auto‐adjusted in response to the output of the PD. The proposed ILFD employs a 2‐bit switched capacitor array to further enhance the entire LR. Implemented in a 65‐nm CMOS process, the experimental results show that the proposed ILFD achieves an LR of 62.3% (10.5–20 GHz) and 51.2% (11.2–18.9 GHz) at 0 and −10 dBm injection power, respectively. The proposed ILFD consumes 3.6 mW from a 0.6 V supply, and the core area is 0.067 mm2.

CMOS Voltage-Controlled Oscillator with Complementary and Adaptive Overdrive Voltage Control Structures

This paper displays a voltage-controlled oscillator (VCO) with high performance implemented in 0.18 µm CMOS. The proposed CMOS VCO adopts a current-reused method, analog coarse and fine tuning mechanisms, and an adaptive overdrive voltage control structure to increase the overall performance, such as the power dissipation, phase noise, and tuning range, and has a robust start-up condition. The current-reused complementary structure with higher transistor transconductances is to save power consumption; the analog coarse and fine tuning mechanisms are to effectively widen the tuning range; and the adaptive overdrive voltage control technique is to change the transconductances of the transistors to improve power consumption by reasonably biasing the gate and body terminals in a class-AB mode to adjust the threshold voltage of the NMOS transistors. The proposed CMOS VCO adopts the class-AB mode to improve the overall performance and the start-up condition. The figure-of-merit (FOM) and FOM with tuning range (FOMT) are used in evaluating the CMOS VCO performance. The measured phase noise at 1 MHz and 10 MHz offsets is –130.34 dBc/Hz and –150.96 dBc/Hz at the 3.38 GHz operating frequency, respectively. The proposed CMOS VCO has a tuning range between 2.85 and 3.62 GHz corresponding to 23.8% for the fifth-generation (5G) wireless communication applications. The proposed CMOS VCO core using a 1.4-V supply consumes 7.5 mW DC power. The FOMs and FOMTs at 1- and 10-MHz offsets are −192.2, −192.8, −199.7, and −200.3 dBc/Hz, respectively, from the 3.38 GHz output frequency.

Low voltage operation of organic thin-film transistor with atmospheric coating of high-k polymer dielectric

We investigated high-k polymers as gate dielectrics to develop an atmospheric-pressure process for organic transistors. A high-k terpolymer, p(VDF-TrFE-CFE), was formed by drop-casting. Self-assembled molecules (SAM) of triptycene derivatives have been utilized as surface modifiers for high-k gate dielectrics to improve the transistor characteristics. High-k terpolymers reduce the operating voltage of organic thin-film transistors (TFTs) by up to 2.5 V to their high capacities. Introducing a SAM onto the gate dielectric surface improved the organic TFTs’ mobility by more than three orders of magnitude. In addition, a terpolymer and a SAM can be formed simultaneously by drop-casting. This atmospheric processing of the gate dielectric is expected to contribute to organic electronics in large-area or mass production, such as roll-to-roll processes.

Increased Threshold Voltage of Amorphous InGaZnO Thin-Film Transistors After Negative Bias Illumination Stress

Increased Threshold Voltage of Amorphous InGaZnO Thin-Film Transistors After Negative Bias Illumination Stress

DETERMINATION OF THE INFLUENCE OF TEMPERATURE AND UV TREATMENT ON THE CHARACTERISTICS OF DIFFERENTIAL ISFET ELECTRODES

The work is devoted to the study of the influence of temperature, UV radiation and a number of additional chemical treatments of crystals of ion-selective field- effect transistors in the electrode assembly in order to carry out appropriate types of chemical-technological treatments of the crystal surface and improve its ability to immobilize biosensitive elements. The influence of ultraviolet treatment on the characteristics of differential pH-FET (threshold voltage and channel current difference) was studied and the long-term effect of such influence was determined. Irreversible in time and significant symmetrical shift of the threshold voltages of both transistors on the crystal in the direction of a decrease in their absolute value from –(1.5–1.6) V to –0.6 V was revealed. It was shown that most electrodes with asymmetric I–V characteristics in the initial state become almost symmetrical after UV treatment, which makes it possible to use them as differential electrodes. It has been established that the relaxation process after UV irradiation is 90% complete within the first 10 days. Limits of permissible heating temperatures of ISFET electrodes of the described design, which do not lead to their failure, have been established. It is shown that the maximum safe heating temperature of the assembled electrodes is no more than 100 ºС when kept for 2 hours, and when heated to a temperature of 130 ºС for 2 hours, the symmetry of the current-voltage characteristics was violated in about 10% of the electrodes, and a drift of the current difference occurred, which lasted for the next 2 days after the temperature treatment. The influence of a number of additional chemical and technological treatments (with the help of a chromium mixture, a «piranha» solution and silanization of the nitride-silicon surface of the crystals) on the parameters of ISFET electrodes was studied. Protocols for effective cleaning and silanization of sensitive surfaces of transistors have been developed. A study on the modification of ISFET electrodes with silver and gold nanoparticles in order to improve their ability to immobilize biological reagents was carried out. It is shown that the use of gold nanoparticles in the composition of the enzyme membrane leads to a significant increase in the operating responses of enzyme biosensors.