Insights into Sub‐Thermionic Transport in Schottky Barrier FETs

Abstract

AbstractBoltzmann carrier statistics restrict the sub‐threshold swing (SS ≥ 60 mVdec–1) and, consequently, the supply voltage (≈ 1 V) of the thermionic transistor. This primary bottleneck results in rapidly increasing power consumption, heating, and associated reliability/scalability challenges as more devices are packed into a small footprint. Despite significant efforts from the device community, a suitable sub‐thermionic alternative is yet to emerge. In this work, an attempt is made to understand the physics of Schottky barrier FETs demonstrating SS < 60 mVdec–1, as evident in some experimental results. Employing the in‐house TCAD tool, the electrostatic potential in the device is accurately modeled with the sweeping gate bias. Next, the Tsu–Esaki model is used to compute the tunneling current. The analysis shows that the steep SS results from an abrupt change in the tunneling barrier profile, from a step‐like to a triangular‐like. However, in the ON regime, the drift component begins to dominate the transfer characteristics. Thus, the subtle interplay between the drift and tunneling components of transport leads to SS < 60 mVdec–1 in OFF‐state with improved in ON‐state. Finally, using the calibrated model, the performance metrics of an all‐2D material‐based CMOS inverter operating at a low VDD ≈ 0.6 V are projected.