Voltage Slope Research Articles

Fault diagnosis of early internal short circuit for power battery systems based on the evolution of the cell charging voltage slope in variable voltage window

Internal short circuit (ISC) is one of the main causes of thermal runaway (TR) accident in power battery systems, to effectively avoid the development of early stage ISC towards TR, this paper innovatively proposes an ISC fault diagnosis method based on the evolution of the cell charging voltage slope (CCVS) in variable voltage window (VVW). Firstly, the ISC characterisation parameter, i.e. CCVS, is extracted through battery cell aging and equivalent ISC experimental studies. This parameter has two advantages: on the one hand, the charging voltage slopes of different cycles of one cell in different voltage windows keep the same evolution law, so that the mechanism of VVW can be established, and the generalisation ability of the algorithm is improved. On the other hand, the charging voltage data of one cell as the research object effectively avoids the interference of inconsistent factors between battery cells. Then, the battery data are preprocessed using wavelet denoising, and a sliding window strategy is introduced to calculate the positional ranking of the CCVS in the historical data, which represents the capacity ranking level of the cell in this charging segment, defined as the capacity rating factor (CRF). Further, a double-layer diagnostic strategy based on the 3 σ criterion and distance factor assessment is used to localise the fault, which can effectively avoid the occurrence of false alarms. Finally, experimental and real-world vehicle data validate the effectiveness of the method, different types of battery data verify the applicability of the method, and the comparison results of the same type of model show that the proposed method is significantly superior in terms of robustness, accuracy and computational efficiency.

Impact of underlap layer on DC and RF/analog performance of asymmetric junctionless dual material double gate MOSFET for low-power analog amplifier design

Impact of underlap layer is analytically investigated on asymmetric junctionless dual material double gate MOSFET (AJDMDG) to reduce subthreshold slope and threshold voltage, which are two essential requirements with shrinking device dimensions to avoid short channel effects. The model utilizes two-dimensional Poisson’s equation with parabolic approximation for determining electrical parameters where dimensional ranges are kept within fabrication limit. Excellent accuracy is found for the obtained analytical outcome, when compared with results obtained from TCAD ATLAS simulator. Comparative study is extended for conventional junctionless DMDG (JDMDG) and underlap asymmetric junctionless single material DGFET (UAJDG) device, having identical dimensional parameters and biasing ranges; where the present structure exhibits superior performance in terms of threshold voltage, subthreshold slope and DIBL of 34.57%, 62.85% and 69.85% respectively compared to JDMDG and 12.50%, 26.08% and 40.25% respectively w.r.t UAJDG structure. Supremacy of the proposed architecture is further established with RF/analog Figures of Merit (FOMs), which are essential for designing low power analog amplifier.

Comparative Cryogenic Investigation of FD-SOI Devices with Doped Epitaxial and Metallic Source/Drain

Defects induced by the source/drain process have a significant impact on the scattering mechanism of PMOS at cryogenic temperatures. Here, the cryogenic characteristics of FD-SOI devices with heavily doped epitaxial source/drain (Epi FD-SOI devices) and metallic Schottky barrier source/drain (SB FD-SOI devices) were investigated from 300 K down to 6 K. The doping profile along the channel was analyzed by TCAD simulation analysis. Experimental comparison of transistor performance at cryogenic temperatures was carried out for these devices with gate lengths (L G ) of 100 nm and 40 nm. The I-V characteristics of the FD-SOI devices were measured with a liquid helium cooling environment. The cryogenic effect of the two types of devices on Key parameters including transconductance (G m ), field effect mobility (μ FE ), threshold voltage (V th ) and subthreshold slope (SS) were systematically analyzed. The doping distribution of the heavily doped epitaxial SiGe source/drain structure were subjected to more Coulomb scattering at cryogenic temperatures, whereas the doping distribution of the Schottky-barrier source/drain structure dictates that the device is mainly subjected to phonon scattering at cryogenic temperatures.

A coordinated voltage control scheme based on linearized power flow functions for non-optimal and optimal problems

This paper proposes a coordinated voltage control scheme for transmission systems based on linearized power flow functions to determine the set points of local control voltage devices. The scheme considers models and interactions between different devices to attain the appropriate performance (non-optimal or optimal) of the whole power system. The sensitivity analysis is used to formulate a partly linearized model that relates the voltage variations of buses to the reactive power variation of synchronous machines, settings of static VAr compensators (SVCs), shunt capacitors susceptance, and tap position of load tap changers (LTCs) to determine the set of the settings of the voltage control devices. Two formulations are proposed by considering the susceptance of SVCs or the slope and reference voltage of characteristics of SVCs as control variables. The developed formulation based on the linearized power flow functions provides the possibility of the practical implementation of the coordinated voltage control scheme, especially the optimal one, by reducing the model complexity and solving time. The performance of the proposed formulations is investigated by some studies of voltage control and an optimally coordinated problem on the IEEE 30-bus and IEEE 118-bus test systems.

Effect of the column design and fabrication method on the reverse recovery characteristics of 1.2 kV SiC-superjunction-MOSFETs

We investigated the effects of the column length and fabrication method of the superjunction (SJ) structure on the reverse recovery characteristics of 1.2 kV silicon carbide (SiC) SJ metal–oxide–semiconductor field-effect transistors (MOSFETs). The voltage slope (dV/dt) and reverse recovery current slope (dir/dt) values during the reverse recovery of the SJ-MOSFETs with the SJ structure formed by Aluminum (Al) ion implantation were comparable to the values of MOSFETs without SJ structure at room temperature (RT), but they increased markedly with temperature. This is caused by the reduced p-column carrier concentration at RT during short recovery transient time due to the deep hole trap (DI center) introduced by ion implantation. At 175 °C, a softer reverse recovery waveform was obtained by shortening the SJ columns. Besides, Al ion implanted SJ-MOSFETs exhibited a weaker current dependence of the reverse recovery charge Qrr at 175 °C indicating a lower carrier injection level compared to the SJ-MOSFETs with the SJ structure formed by trench formation and epitaxial growth. This is caused by the short carrier lifetime of the SJ columns due to the Al ion implantation defects. The short and Al ion implanted SJ columns are effective for soft reverse recovery characteristics in SiC-SJ-MOSFETs.

Frequency Stability Control Strategy for Voltage Source Converter-Based Multi-Terminal DC Transmission System

The voltage source converter-based multi-terminal DC transmission (VSC-MTDC) system can use additional frequency control to respond to the frequency change of faulty AC system. However, the control coefficient of traditional additional frequency control is mostly fixed, and the control flexibility is insufficient, so it cannot be adjusted adaptively according to the frequency change of the system. Therefore, a frequency control strategy of the VSC-MTDC system based on fuzzy logic control is proposed. Based on the DC voltage slope controller, this strategy introduces an additional frequency controller based on fuzzy logic control, takes the frequency deviation and frequency change rate as the additional controller input, and dynamically adjusts the control quantity through the fuzzy logic control link to realize the adaptive adjustment of the VSC-MTDC system to the AC system’s frequency. Finally, a three-terminal flexible HVDC system is built on the PSCAD/EMTDC simulation platform for simulation verification. The results show that the proposed control strategy can effectively use the flexible DC system to support the frequency of the AC system and significantly improve the frequency stability of the faulty AC system.

Effect of temperature modulation on the performance of top contact bottom gate organic thin film transistor

This research article investigates the influence of temperature variations on the performance parameters of Top Contact Bottom Gate (TCBG) Organic Thin Film Transistors (OTFTs). Employing the Arrhenius equation and Schottky emission model, the study explores temperature-dependent charge carrier mobility and injection mechanisms. Analyzing a wide range of parameters, the research unveils a complex interplay between temperature and OTFT behavior. The linear and saturation mobilities exhibit a decline due to enhanced carrier-phonon interactions and lattice vibrations. Transconductance and ION/IOFF ratio display a concomitant decrease at higher temperatures, indicative of the heightened susceptibility of OTFT performance to temperature fluctuations. The depreciation in subthreshold slope and threshold voltage with rising temperatures underscores the influence of temperature on trap states. The research emphasizes the importance of considering temperature’s impact during OTFT design for diverse applications, enhancing the reliability and functionality of organic electronic devices.

High Sensitivity of Dielectrically Modulated Tunnel Field Effect Transistor for Biosensor Applications.

The Dielectrically Modulated Full Gate Tunnel Field Effect Transistor (FET) with dual nanocavities, as described in the paper, is a novel device designed as a label-free biosensor for detecting cancer cell biomolecules. This biosensor utilizes the principles of field-effect transistors and incorporates nanocavities to enhance the detection sensitivity. The simulations are conducted using the Silvaco Atlas model, which allowed for the analysis of the device's electrical characteristics in the presence of various cancer cell biomolecules. The performance of the proposed device is evaluated using several sensing metrics, including current, threshold voltage, and subthreshold slope. These metrics are examined to assess their sensitivity to the presence of different cancer cell biomolecules. By analyzing these electrical characteristics, we can able to determine the device's ability to detect and differentiate between specific biomolecules associated with cancer cells. One important aspect discussed in the paper is the incorporation of nanocavities in the device design. These nanocavities have a significant impact on enhancing the sensing capabilities of the biosensor. The paper also introduces the concept of the filling factor parameter, which describes the fraction of the nanocavity volume occupied by the cancer cell biomolecules. This parameter plays a crucial role in achieving optimal sensing performance. Overall, the paper presents a comprehensive analysis of the proposed Dielectrically Modulated Full gate Tunnel FET embedded with dual nanocavities as a label-free biosensor for cancer cell biomolecules. The simulations conducted using the Silvaco Atlas model provide valuable insights into the device's electrical characteristics and its sensitivity to different biomolecules. The study emphasizes the significance of nanocavities and their filling factor parameter in achieving enhanced sensing performance for cancer cell detection.

Slope Efficiency and Voltage Reduction at High Current Densities in AlInGaAs Diode Lasers

Slope Efficiency and Voltage Reduction at High Current Densities in AlInGaAs Diode Lasers

FinFET Technology: Modeling and RF Characterization for 5nm Node Technology: A Review

The study offers new methods for understanding and simulating the radiofrequency, analog, and thermal characteristics of the FinFET at the 5nm CMOS technology node. The results of the thermal assessment show that changes in temperature have an effect on the threshold voltage and sub-threshold slope (SS). The maximum oscillation frequency and cut-off frequency of an n-FinFET RF device with a single gate contact are revealed by the RF investigation. Additionally, the study provides information about the device-level temperature sensitivity of the analog and RF Figures of Merit (FoMs) for the 5nm technology. The industry-standard BSIM-CMG model is adjusted to include the effects of self-heating (SH) and parasites in order to improve model accuracy. The updated BSIM-CMG model increases accuracy by taking self-heating and parasite effects into account. Effective heat pathways for lowering junction temperature are found by employing vias on silicon and stacks of conductive materials made of metal. It should be remembered, though, that using these heat pathways could raise parasitic capacitance and negatively impact the circuit's functionality. Keywords: RF Characterization, Thermal Impact, Self-Heating, Figure of Merit, FinFET, Analog Characteristics.

Reaction mechanisms of NASICON-type Na4MnV(PO4)3/C as a cathode for sodium-ion batteries

NASCION-type Na4MnV(PO4)3/C was synthesized through a sol–gel method. Two Na+ ions can reversibly (de)intercalation from/into the unit structure, with a reversible capacity of 106.7 mAh/g. The charge–discharge curves show a voltage slope at 3.4 V, and a plateau at 3.6 V. To elucidate the sodium storage mechanisms, the structure evolution and electron transfer are demonstrated using in-situ X-ray diffraction and ex-situ X-ray absorption spectroscopy. It is found that at different stage of the electrochemical process, it undergoes different phase reaction process with different redox couples. A single-phase reaction occurs when the first sodium-ion extracted from Na4MnV(PO4)3 with a V3+/V4+ redox, while a two-phase reaction takes place when the second sodium-ion extracted with a Mn2+/Mn3+ redox. Galvanostatic intermittent titration technique, GITT, indicates the single-phase reaction process shows a faster kinetic compared to the two-phase reaction process. These findings between the kinetics, chemical and structural evolution provide new insight into the sodium storage mechanisms of NASICON-type cathode, and further the understanding of other materials for sodium-ion batteries.

Advanced Method for Voltage Breakdown Analysis of PEM Water Electrolysis Cells with Low Iridium Loadings

Proton exchange membrane water electrolysis (PEMWE) is an established technology for hydrogen production. To meet the increasing demand and further reduce costs, there is a growing interest in reducing the iridium (Ir) loading. In recent works the complex interface between porous transport layer (PTL) and catalyst layer (CL) was identified as pivotal for PEMWE performance. In this study, this interface was systematically investigated for various Ir loadings and PTL types using a voltage breakdown analysis (VBA) method to differentiate between different sources for overpotential. As expected, the oxygen evolution reaction (OER) overpotential increases with decreasing Ir loading, but its extent depends on the CL/PTL interfacial contact area and the in-plane electrical conductivity of the CL. If the latter is low, this can be partly compensated by using a proper PTL counterpart. However, especially when using low Ir loadings, the VBA method results in inconclusive OER kinetic parameters such as the apparent exchange current density. Therefore, the constant Tafel slope voltage breakdown analysis (CT-VBA) method is proposed considering possible mass transport losses even at relatively small current densities within the Tafel fit regime. These findings provide insights to tackle challenges associated with reducing Ir loading.

Influence of Inverter Voltage Switching on Windings of Asynchronous Motor

Focus on the stator winding insulation of asynchronous motor, the transition process of the pulse voltage output by the frequency converter was analyzed, the voltage equivalent mathematical models and simulation model of the stator winding, reactor and cable were established. For rolling mill in metallurgical industry, the different voltage slope was verified by using real high-power asynchronous motor and frequency converter for pulse voltage test. Aiming at the voltage oscillation caused by different cables length, the second order system fitting was used to analyze the voltage spectrum characteristics, and the reactor’s suppression effect for voltage oscillation was also verified.

Fabrication and Characterization of Self-Aligned WSe2 p-Type Field-Effect Transistor

Semiconducting transition metal dichalcogenides (TMDCs) have been growing interests as channel materials in field effect transistors (FET) for next generation low power digital electronics. [1]. Since a complementary metal oxide-semiconductor (CMOS) inverter constructed from pairs of n-type and p-type FETs is a fundamental building blocks in modern digital electronics [2], implementation of both n-type and p-type FETs with semiconducting TMDCs is of particular importance [3]. Among various semiconducting TMDCs, tungsten diselenide (WSe2) is a promising candidate for constructing a CMOS inverter because of its high mobility, symmetric electron and hole effective mass and ambipolar transport [4]. These prominent features of WSe2 is suitable for an application to CMOS inverter.One of the significant challenges is to develop a top gate and top contact FET structure with WSe2 for CMOS device integration on the same wafer. In addition, it is desirable to minimize the access region between channel and S/D contact because this access region served as a series resistance to channel resistance, resulting in the lower drain current in FET. This study reports a self-aligned process to fabricate top gate and top contact WSe2 p-type FET. In this self-aligned structure, the gate electrode and source/drain contact edges are automatically positioned and hence there are no overlap or access region between the gate and source/drain. The feature of this proposed method is that the gate stacks was utilized as a mask for self-aligned formation of WOx, which is source/drain contact for efficient hole injection [5]. The focus on this study is the impact of self-aligned structure of p-type WSe2 FET on the electrical characteristics. The effectiveness of proposed process was experimentally demonstrated by the fabrication and characterization of device.Figures 1 shows the self-aligned fabrication process of p-type WSe2 FET. 20 nm-thick SiO2 was formed by dry oxidation of p+-Si substrate. The mechanically exfoliated multi-layer WSe2 was transferred by PDMS stamp. Next, 15 nm-thick Al2O3 was prepared by ALD at 200 oC with H2O. Then, Nickel (Ni) metal was deposited by RF sputtering on Al2O3. Ni metal was patterned for gate electrode with conventional lithography process. After that, A2O3 layer was removed by wet etching. Subsequently, substrate was exposed to oxygen radicals to form WOx used as source/drain contact at surface of WSe2. Second layer of Al2O3 was deposited as an encapsulating passivation layer. After the contact hole opening, the electrical contact pad was fabricated. Finally, forming gas (N2 : H2 = 97 % : 3 %) annealing was performed at 200 oC for 30 min. The top gate length was 5 μm. The gate width was estimated to be 40 μm by optical microscope. The electrical characteristics were measured with a manual probe station in an atmospheric pressure without inert gas purge at room temperature using a precision semiconductor parameter analyzer (Agilent 4156 C).Figures 2 shows the Id–Vg characteristics of fabricated FETs for (a) back gate operation and (b) top gate operation. Representative Id–Vg characteristics of p-type FETs were observed irrespective of back gate and top gate operation. The on/off ratio of about 106 ~ 107 order were obtained for both back gate and top gate operation. Furthermore, the threshold voltage and sub-threshold slope were modulated by varying the substrate bias during gate sweep.This study opens up interesting directions for the research and development of TMDC-based devices.AcknowledgmentsThis study was supported by a JSPS Grant-in-Aid for Scientific Research (C) (Grant No. 20K04616), a research grant for Tokyo Tech Challenging Research Award, the Samco Foundation and a research grant for Suematsu Award.

Operational Transconductance Amplifier Designed with Experimental Omega-Gate Nanowire SOI MOSFETs

The nanowire omega-gate technology is one of the possible technologies to replace the FinFET one in the semiconductor chip market. The omega-gate nanowire SOI MOSFET is considered a triple plus gate device, near the gate-all-around performance (figure 1) [1]. Due to the omega gate structure this device presents a better gate to channel electrostatic coupling than the FinFET devices, resulting in a greater immunity to short channel effects [1,2].The Operational Transconductance Amplifier (OTA) is a frequently used analog block in the integrated circuits. The studied OTA consists in a two-stage amplifier, where the first stage is a differential amplifier with active load and the second one is a common source amplifier, as can be seen in figure 2. This analog block is biased through the current source and the bias current is mirrored for each stage. In addition, negative feedback is used between the first and second stages with a compensation capacitor (miller capacitor) in order to stabilize the amplifier response.In this work, an OTA circuit is designed with SOI omega-gate nanowire experimental transistors. In order to find the best device to be used in the project, some measurements were carried out of several nanowire devices with different channel lengths (ranging from 20 nm to 200 nm). The schematic structure of the measured devices is presented in figure 3 [2]. Basic device parameters such as: transconductance (gm), output conductance (gd), Early voltage (VEA), threshold voltage (VT), transistor efficiency (gm/ID) and subthreshold slope (SS) were analyzed.The model of the experimental omega-gate transistors was performed using the Look Up Table (LUT) method. The capacitance measurements of the nanowire transistor were also considered, to simulate the frequency responses more faithfully. The simulator used to design the OTA circuit was Cadence using the Verilog-A language. It was obtained the main figure of merit of this block like voltage gain (Av), gain-bandwidth product (GBW), phase margin and power.A transistor efficiency (gm/ID) near 8 V-1 was chosen in order to compare the performance of OTA designed with omega-gate nanowire devices (NW-OTA) of this work with anothers OTAs designed with triple gate FinFETs (FinFET-OTA) and with nanosheets (NS-OTA) from the literature (Table 1) [3,4].Table 1 shows that the phase margin is close to 60o in all cases, ensuring the stability of the circuit. The NW-OTA presents higher voltage gain compared to FinFET-OTA due to the better gate to channel coupling. The NS-OTA presents the highest voltage gain of all cases, but it is the more expensive technology [4]. When GBW is analyzed for all 3 designs, the NW-OTA shows better results than the NS-OTA, using the same load capacitance of 200fF, thanks to the lower miller capacitance (Cc) required to keep the frequency behavior. The FinFET-OTA shows the best result in relation to GBW, but the FinFET-OTA project doesn’t consider a load capacitance, making the comparison unfair [3].Figure 4 shows the gain and phase of the OTA using a SOI omega-gate nanowire transistors.In summary, the OTA designed with SOI omega-gate nanowire technology presents a better performance than FinFET one, can be implemented in a smaller area on the chip (smaller Cc capacitor and smaller number of fins in parallel) and it is a cheaper option compared to nanosheet one. Figure 1

An Optimized Switching Strategy Based on Gate Drivers with Variable Voltage to Improve the Switching Performance of SiC MOSFET Modules

This paper proposes an optimized switching strategy (OSS) based on a silicon carbide (SiC) MOSFET gate driver with variable voltage, which allows simultaneous variations in several different parameters to optimize the switching performance of semiconductor devices. As a relatively new device, the SiC MOSFET shines in the field of high power density and high-frequency switching; it has become a popular solution for electric vehicles and renewable energy conversion systems. However, the increase in voltage and current slope caused by high switching speeds inevitably increases the overshoot and oscillation in a circuit and can even generate additional losses. The principle of this new control strategy is to change the voltage and current in the turn-on and turn-off stages by changing the gate driver’s voltage. That is, we reduced the drive’s voltage after a certain time delay and maintained it for a period of time, thus directly controlling the slopes of di/dt and dv/dt. This study focused on the optimization of the SiC MOSFET by changing the time delay preceding the decrease in the voltage of the gate driver, analyzing and calculating the optimal time delay before the decrease in the voltage of the gate driver, and verifying the findings using LTspice simulation software. The simulated results were compared and analyzed with hard-switching strategies. The results showed that the proposed OSS can improve the switching performance of SiC MOSFETs.

State of health estimation for lithium-ion batteries using Gaussian process regression-based data reconstruction method during random charging process

State of health (SOH) estimation is a critical technology to guarantee the safe and reliable operation of battery energy systems. Data-driven methods have been widely studied in the field of lithium-ion battery SOH estimation. However, random charging in real operating scenarios will result in difficult extraction of health features, which in turn limits the online application of data-driven methods. In this paper, a SOH estimation method using a piece of random charging data is proposed. In random charging scenarios, the health features screened within the predefined charging range are easily lost. For this reason, the partial charging data is reconstructed by the Gaussian Process Regression (GPR) model to intelligently supplement the health features that are not sampled. In terms of health feature selection, this paper selects the charging time sequence within a voltage interval as the input of the Long-Short-Term Memory (LSTM) estimation model, so that the complicated feature extraction work can be avoided, such as the peak of incremental capacity (IC) curve, the slope of the charging voltage and so on. The experimental results show that the data reconstruction method based on the GPR model can reconstruct the missing charging data accurately under a large number of simulated random charging data, and the reconstruction error of the charging data under two types of aging paths is less than 4.30%. Finally, using most known health features and a few reconstructed health features within certain charging intervals, the proposed GPR-LSTM method achieves a root-mean-squared percentage error (RMSPE) of 2.51% in SOH estimation for the two well-known laboratory datasets, and compared to 3.89% for the IC peak feature-based method, a reduction by 1.47%. Meanwhile, for a real-world battery data, the RMSPE of the proposed method is below 3%, illustrating the usefulness of the proposed method under the on-road conditions.

Design and Performance Analysis of Negative Capacitance Effect in the Charge Plasma-Based Junction-Less Vertical TFET Structure

In this paper, a negative capacitance (NC) effect in series with normal oxide capacitance is first time introduced to design negative capacitance charge plasma-based junction less vertical TFET structure (NC-CP-JL-VTFET). The introduced negative capacitance enhances the overall gate capacitance and hence gate capacitive coupling and thus renders high current capabilities with reduced sub-threshold slope and threshold voltage. With the use of negative capacitance along with oxide capacitance, it has been seen that the same drain current is achieved at lower gate voltage as compared to without use of negative capacitance and since the voltage scaling is done considerably, the dynamic power dissipation in circuit application can be reduced significantly. To generate the negative capacitance during the device operation; ferroelectric material [Formula: see text](VDF-TrFE) poly(vinylidene fluoride-trifluoro ethylene) is used in stack with SiO2 gate oxide. Various performance parameters of the designed structure such as electron–hole concentration in the tunneling junction, electric field, surface potential, electron–hole quasi-Fermi variation, and drain current variation are investigated and compared with the results of without considering the ferroelectric material in the gate oxide. The variation of the ferroelectric thickness on the device performance is also investigated. The investigation exhibits significant improvement in the drain current and in the other parameters as well. These improvements are seen because of higher capacitive coupling and these effects are further responsible for more energy band bending which in turn govern high electron tunneling. Due to the existence of negative capacitance, the peak value of the electric field gets doubled while the surface potential increases 44% from the normal structure.

Response behaviour of proton exchange membrane water electrolysis to hydrogen production under dynamic conditions

Hydrogen production via proton exchange membrane water electrolysis (PEMWE) coupled with renewable energy sources is gaining considerable attention due to its high current densities and flexible responses. This study investigated the voltage responses of PEMWE under dynamic conditions. Three comprehensive performance parameters were adopted to determine the response behaviours of PEMWE devices, including the total response time (TRT), the voltage stability (Vmax - Vmin), and the difference between the voltages seen for dynamic and static conditions (ΔV = Vdynamic - Vstatic). The obtained results showed that with small step currents (ΔI = 1 A) and low currents (I < 9 A), PEMWE presented better responses. The TRT was less than 30 s, (Vmax - Vmin) was less than 10 mV, and ΔV was less than 20 mV. Increasing the amplitude of the step current increased the response time and reduced the voltage stability during electrolysis. The Joule heat produced by the inner resistance have been responsible for the different response behaviours of the PEMWE devices. A durability test showed that after a square wave operated for 300 h, significant degradation of the PEMWE response was observed by comparing the voltage response parameters. Electrochemical characterization studies indicated increases in the static voltage, resistance, and Tafel slope, which were consistent with the degradation of the PEMWE response.

Active Current Balancing for Paralleled SiC Semiconductors in Time-Staggered Switching Mode

The steep voltage slopes of today's wide-bandgap, fast-switching power semiconductors — like SiC and GaN — lead, among other challenges, to reflection on long cables and thereby overvoltage at inductive loads. To apply this technology to motor drives without specially reinforced insulation the voltage slopes need to be reduced. This article presents a new low-loss countermeasure, which involves the parallel connection of two half-bridges via an interphase transformer. Undesired components in the cross-current of the interphase transformer occur due to non-idealities in the voltage symmetry. The resulting additional magnetization can cause the core to saturate. Influences on the converter voltage due to various parasitic influences are described. Especially aspects relevant for dimensioning the magnetic core of the interphase transformer are emphasized. Also, this article describes an approach to deal with the undesired cross-current components using two different closed-loop control concepts. The control uses a special differential-mode shunt for a dedicated measurement of the cross-current mean value. Both control concepts are verified and compared on a 500-kVA SiC inverter test bench, using measurements of the controlled current.