Voltage Slew Rate Research Articles

Sample Voltage Dead-Beat Control Based on Differentiative Voltage Prediction and Switching-Cycle Extension for DC-DC Converters

In this paper, a sample voltage dead-beat control based on differentiative voltage prediction (DVP) and switching-cycle extension (SCE) is presented to achieve optimal transient response for DC-DC converters under discontinuous conduction mode (DCM) operation. Firstly, to improve load transient response, a DVP method is proposed to estimate the load. With the estimated load, the controller realizes load current feedforward and thus improves the transient response with a wide load range. Secondly, an SCE strategy is proposed to enlarge the output current range and output voltage slew rate, both of which have limited value under conventional digital pulse width modulation (DPWM). When the output current reaches the limited value, the proposed strategy increases the switching cycle to enlarge the current range without losing DCM operation. Finally, combining DVP with SCE, the converter not only achieves optimal response in large signal transients, but also doubles the load range in DCM operation.

Improved frequency compensation technique of three stage amplifier using class AB flipped voltage follower and slew rate enhancer circuit

In this work, two frequency compensated three stage amplifiers are proposed for 20 pF and 30 pF capacitive load. Both the proposed circuits utilize class AB Flipped Voltage Follower (FVF) along with Reversed Nested Miller Compensation (RNMC) to address RHP zero issue. Further, the proposed circuits 1 and 2 employ a slew rate enhancer circuit to improve the slew rate. Additionally, both the circuits also make use of feed forward path to increase the large signal response. The simulations are performed using TSMC 0.18 µm CMOS process in Tanner tool to examine the functionality and performance of the proposed amplifiers. The proposed amplifiers exhibit GBW of 25 MHz with phase margin of 82° at 20 pF load, whereas it is 22 MHz with phase margin of 79° at 30 pF load. Moreover, DC gain is 102 dB and 110 dB for the proposed amplifier-1 and 2 respectively. Further, maximum slew rate is 10.8 V/µS at 20 pF load while it is 10.56 V/µS at 30 pF load. The maximum common mode rejection ratio and power supply rejection ratio are examined to be 87.8 dB and 87.4 dB respectively. Corner analysis has been performed to look into the process variations to verify the robustness of the proposed amplifiers.

Ultra-fast generator for impact ionization triggering

In recent years, it has been discovered that thyristors triggered in impact ionization mode find their dI/dt capability boosted by up to three orders of magnitude. This innovative triggering requires applying an important overvoltage on the anode-cathode of the thyristor with a slew rate > 1 kV/ns. Compact pulse generators based on commercial off the shelf components (COTS) would allow the spread of this technology into numerous applications, including fast kicker generators for particle accelerators.Our approach for such a compact pulse generator begins with a HV SiC MOS with an ultra-fast super-boosting gate driver. Super boosting in the gate of a 1.7 kV rated SiC MOS allows to reduce its rise time by a factor of ≈ 30 (datasheet tr = 20 ns vs. measured tr < 680 ps), resulting in an output voltage slew rate > 1 kV/ns and an amplitude > 1 kV.Next, additional boosting is obtained by a Marx generator with D2PAK thyristors, reaching an output voltage slew rate > 16 kV/ns. Finally, creating sufficient current necessary for the triggering of a big thyristor presents a new challenge. In this paper, we present an upgraded board design with a higher current output capacity.

A Fast Dielectric Response Measurement Instrument With Dynamic Power Supply Tracking and Active Suppression of Temperature Fluctuations

This paper proposes a fast frequency domain dielectric spectroscopy (FDS) test scheme for diagnosing oil-paper insulation. The high-voltage output section introduces dynamic power supply tracking (DPST) and cascading techniques to generate high-voltage excitation signals. The DPST can increase the amplifier's voltage slew rate (SR) from 13 V per microsecond to 36.3 V per microsecond without crossover distortion. In the micro-current measurement section, the error active suppression structure of bias current and bias current under time-varying temperature conditions is proposed to improve the temperature stability of the measurement circuit. The fast testing technology shortens the test period by 65% in the low-frequency band by using the method of multi-frequency signal synthesis and partial cycle waveform fitting. The experimental results show that the total harmonic distortion and noise (THD+N) of the output voltage of the instrument are less than or equal to 0.078%. The voltage range is 780 Vpp. The standard deviation of current is less than 1.5%, and the standard deviation of tan δ is less than 1.7%, which verifies the stability of the designed instrument.

Circuit Design Modernization of Operational Amplifiers for Increasing Slew Rate of Output Voltage

To meet the existing needs of the domestic market of radio electronic equipment in high-speed wideband operational amplifiers, it was previously proposed to use the MH2XA031 master slice array containing complementary bipolar transistors, together with the developed circuits of the OAmp9 high-speed operational amplifier and the OAmp10 precision operational amplifier with unified cascades and the ability to program parameters such as current consumption, maximum output current, bandwidth, slew rate. The article discusses the increase in the performance of these operational amplifiers by reducing the parasitic collector capacitance of transistors by applying a reverse bias voltage to OAmp9 and using correction circuits in OAmp10, which made it possible to increase the output voltage slew rate by 29 % in the first case and 3.1 times in the second. The electrical circuits and the results of circuit simulation of the upgraded amplifiers, called OAmp9M, OAmp10M, are presented, which are respectively characterized by a zero offset voltage of 0.35 and 0.03 mV, a voltage gain of 2.7 · 103 and 3 · 105, the gain bandwidth product 161 and 68 MHz, output voltage slew rate 708 and 64.5 V/µs.

Detection and Location Approach to Incipient Grounding Defect in Transformer Winding Based on Sequence Voltage Ratios at PV Inverter Switching Frequency

Silicon Carbide (SiC) power devices are used increasingly in photovoltaic (PV) inverters, with the high switching frequency (fs) and voltage slew rate. For the SiC- based-inverter-fed transformer, the ageing of groundwall insulation is aggravated and the grounding defect should be reliably detected at incipient stage. In this paper, a novel approach based on negative and zero sequence voltage components at fs is proposed to realize comprehensive online monitoring of incipient grounding defect. At fs, the equivalent sequence circuit of the PV distribution network is built and the mechanism and characteristics of sequence voltage components are investigated in scenario of the high-resistance grounding defect. The effects are distinguished caused by defect from imbalanced operation. Two sequence voltages ratios are developed to identify the occurring phase and to evaluate the defect location and severity. The MATLAB&#x002F;Simulink model and the SiC-based- inverter platform are built for simulation and online experimental validation, respectively. The proposed online approach can sensitively detect and locate the defect with grounded resistance above 1 k&#x03A9; from each winding. Due to its noninvasiveness nature and convenient implementation, the operating reliability of the PV distribution network can be enhanced effectively.

СХЕМОТЕХНИЧЕСКИЕ МЕТОДЫ ПОВЫШЕНИЯ БЫСТРОДЕЙСТВИЯ ОПЕРАЦИОННЫХ УСИЛИТЕЛЕЙ НА ОСНОВЕ «ПЕРЕГНУТОГО» КАСКОДА

Three circuit techniques are proposed that provide (with simultaneous use) an increase bymore than two orders of magnitude of the maximum output voltage slew rate (SR) of microelectronicoperational amplifiers (op-amps) based on bipolar transistors with a classical architecture,designed to operate in automatic control systems, radio engineering and communications, forexample, as drivers for ultra-high-speed analog-to-digital converters (EVIOAS150, EVIOAS350,AD9208, AD9691, 1273PV14, etc.). The considered op-amps contain a cascode input stage with anon-linear correction of the pass-through characteristic and a tracking circuit that increases theattenuation coefficient of the input common-mode signals and the noise suppression coefficient onthe power buses, as well as an intermediate stage based on a “folded” cascode. The use of a"folded" cascode makes it possible to increase the efficiency of using power supply voltages, aswell as to increase the unity gain frequency of the corrected op-amp. However, such an intermediatestage is an essential non-linear link that limits the maximum output currents that recharge theop-amp correction capacitor. The results of computer simulation of two modifications of theAmpSR1, AmpSR2 op amps, which differ from each other in the structure of a nonlinear parallelchannel, which eliminates the dynamic overload of a "folded" cascode, are presented. The relevanceof the research performed is related to the problems of import substitution in the class ofhigh-speed op-amps and the lack of new and promising ideas for increasing the SR of the op-ampbased on the simultaneous use of non-linear and differentiating transient correction circuits in thelarge signal mode among analog circuit designers. The considered circuit techniques are alsoeffective when using CMOS technological processes.

Ultra-fast generator for impact ionization triggering

Impact ionization triggering can be successfully applied to standard thyristors, thus boosting their dI/dt capability by up to 1000x. This ground-breaking triggering requires applying significant overvoltage on the anode-cathode of a thyristor with a slew rate > 1 kV/ns. Compact pulse generators based on commercial off-the-shelf (COTS) components would allow the spread of this technology into numerous applications, including fast kicker generators for particle accelerators. In our approach, the beginning of the triggering chain is an HV SiC MOS with an ultra-fast super-boosting gate driver. The super boosting of a 1.7 kV rated SiC MOS allows to reduce the MOS rise time by a factor of > 26 (datasheet tr = 20 ns vs. measured tr < 800 ps), resulting in an output voltage slew rate > 1 kV/ns and an amplitude > 1 kV. Additional boosting is obtained by a Marx generator with GaAs diodes, reaching an output voltage slew rate > 11 kV/ns. The final stage will be a Marx generator with medium size thyristors triggered in impact ionization mode with sufficient voltage and current rating necessary for the triggering of a high power thyristor. This paper presents the impact ionization triggering of a small size thyristor.

Characterization of Partial Discharges in High-Frequency Transformer Under PWM Pulses

Partial discharge (PD) is a phenomenon often occurring in insulation system defects (cavities), which can significantly affect life and reliability. While broad knowledge on PD phenomenology of high-frequency transformers (HFT) has been achieved under ac sinusoidal voltage, much less work has been done to infer PD behavior under emerging high frequency pulsewidth modulation (PWM) operation conditions. An impediment has been the limited appropriate test equipment. A recently developed novel ±5 kV GaN-based high-frequency PWM supply with controllable <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dV/dt</i> , voltage level and frequency has been developed. This article explores the application of these measurements to the testing of materials in this electrical environment. Two commonly used windings for HFT were tested under different applied voltage magnitudes, frequencies, and slew rates. According to the test results, at high frequency (up to 50 kHz) the electric field generated by space charge deposited by PD occurring during previous PWM pulses plays an important role in PD behavior. The frequency dependent permittivity of the insulation material can also affect PD measurement results.

Lithium Battery Model and Its Application to Parallel Charging

A new SOC (State-Of-Charge)–VOC (Voltage-of-Open-Circuit) mathematical model was proposed in this paper, which is particularly useful in parallel lithium battery modeling. When the battery strings are charged in parallel connection, the batteries can be deemed as capacitors with different capacitances, and the one with larger capacitance always obtains the higher current. According to this mathematical model, the parallel battery charging with different peak capacitances can result in different voltage slew rates on different battery strings during the constant current control. Different parallel battery strings are charged with different currents, of which the battery string under higher current can induce higher power loss and higher temperature. The conventional solution can use this model to switch the constant current charging into the constant voltage charging with the correct timing to avoid overcurrent charging. Other battery pack protection methods including current sense resistor, resettable thermal cutoff device, or resettable fuse can also use this mathematical model to improve the protection. In the experiments, three kinds of batteries including LiFePO4 battery, EV Type-1 battery, and ternary battery were examined. The experiments showed good consistency with the simulation results derived from the mathematical model.

Novel Characterization of Si- and SiC-Based PWM Inverter Bearing Currents Using Probability Density Functions

The high frequency PWM voltage pulses from a two-level six-switch inverter produce a common-mode voltage in an electric machine’s windings, a fraction of which appears on the machine shaft due to electrostatic (capacitive) coupling. When the shaft voltage exceeds the dielectric strength of the bearing lubricating grease, electric discharge machining (EDM) electrostatic discharges occur within the bearing, which can lead to premature failure. According to pulsed dielectric theory, the breakdown voltage across a dielectric increases with an increase in voltage slew rate (dv/dt). Therefore, the faster voltage rise times of wide bandgap devices are expected to produce higher magnitude shaft voltages and EDM bearing currents. This paper presents circuit modeling of EDM currents and compares the shaft voltage and bearing current amplitudes of silicon- and silicon carbide-based PWM inverters through experimental measurements and a statistical analysis using probability density functions. The statistical analysis provides insights regarding the correlation between bearing failure and the number of damage causing discharges over time which is a key step in developing bearing lifetime prediction models.

Impact of Parasitic and Load Current on the Attenuation of Motor Terminal Overvoltage in SiC-Based Drives

In SiC-based adjustable speed drives, the high voltage slew rate ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$dv\!/\!dt$</tex-math></inline-formula> ) of the switching transitions results in excessive overvoltage at the motor terminals due to the reflected voltages across the drive power cables. Besides the cable length, the switching rise/fall times of the voltage pulses are a key parameter to quantify the motor overvoltage in pulsewidth modulation (PWM) inverter-fed drives. These times are varying depending on the load current and parasitic elements of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s, that is, a standard two-level converter typically results in a nonuniform overvoltage envelop at the motor terminals. This article analyses the switching mechanism of the two-level converter considering the impact of SiC parasitic elements and load current showing how they affect the motor overvoltage in cable-fed drives. The analysis is then extended to the mitigation of the motor overvoltage using quasi-three-level (Q3L) modulation as a candidate filter-less approach with a T-type converter. The theoretical analysis is validated through experimental tests by using the Q3L T-type converter. The analysis and results show that the instantaneous load current value critically determines the peak motor overvoltage, while it allows either a full or partial overvoltage mitigation when the Q3L modulation is adopted.

Effect of Voltage Slew Rate on Partial Discharge Phenomenology During Voltage Transient in HVDC Insulation: The Case of Polymeric Cables

In this article, the partial discharge (PD) behavior inside a cavity embedded in a dc cable, upon application of a voltage step from transient till steady-state dc, is analyzed as a function of voltage slew rate. The variation of PD characteristics, namely PD charge amplitude and repetition rate, is modeled and fitted from the beginning of the voltage transient to dc steady state, and the extent of aging associated with PD at different slew rates is evaluated through a cumulative damage concept. Two possible scenarios for the electric field transient and PD repetition rate are presented, differing for the ratio of conductivity and permittivity of dielectric and cavity medium. Having demonstrated that the proposed PD repetition rate model can predict reasonably the experimental results, it is shown that slowing down voltage rise time during, e.g., cable energization or voltage polarity inversion, could be beneficial to reduce the accelerated aging extent associated with voltage transients.

Frequency-Selective MHz Power Amplifier for Dielectric Barrier Discharge Plasma Generation

Plasma-assisted nitrogen fixation at atmospheric pressure is a clean and decentralized method for fertilizer production. Among many different plasma discharge types, dielectric barrier discharge (DBD) is one of the few that can generate high output of nitrogen compounds at atmospheric conditions for fertilizer usage. Most DBD generators operate at kHz switching frequencies, however, previous research has found that discharge activities occur at the intervals of the greatest voltage slew rate. The finding implies that operating at higher frequencies can lead to more discharge activities and higher plasma generation. This paper presents a MHz Class E power amplifier with frequency selection to generate DBD plasma at two distinct frequencies. The power amplifier achieves a peak efficiency of 91.5% and outputs 600 W at frequencies of 12.4 MHz and 15.5 MHz.

Dynamic Response of Buck Converter With Auxiliary Current Control: Analysis and Design of Practical Implementation

An in-depth analysis on the load transient operation of a buck converter with auxiliary current control is presented in this article. The analysis quantifies the effects of nonideal characteristics, such as the equivalent series resistance, inductor current and output voltage ripples, time delay, and slew rate of the load current, on the fluctuation of the output voltage in a practical implementation. The analysis results reveals that some of the non-idealities may cancel each other out and become negligible in the implementation. A design considering the nonidealities can achieve the transient-wise capacitor charge balance of the output capacitor and minimize the output voltage deviation during the load transient. The agreement between the simulation and experimental results validates the effectiveness and precision of the proposed analysis and design.

Influence of Rise Time and Fall Time on Surface Discharge Characteristics of PEEK Under Positive Repetitive Square Voltage

In this paper, the surface discharge current pulses of PEEK (polyether-ether-ketone) under positive repetitive square voltage are measured. The effects of voltage rise time and fall time on pulse parameters of discharge current, instantaneous voltage of discharge and time-lag of discharge are analyzed in detail. The results show that the amplitude of discharge current and the instantaneous voltage of discharge decrease, and the time-lag of discharge and the dispersion of time-lag increase with the increase of voltage rise time. With the increase of voltage fall time, the amplitude of discharge current decreases and the instantaneous voltage of discharge, the time-lag of discharge and the dispersion of time-lag increase. To analyze the influence mechanism of voltage rise time and fall time on surface discharge, the accumulation of surface charge under repetitive square voltage is regarded as a periodic process. Besides, the correlation between forward discharge and back discharge in the process of discharge is analyzed, and the development of discharge is analyzed by using the time-lag theory. Furthermore, the relationship between instantaneous discharge voltage and voltage slew rate is revealed, and the surface charge accumulation processes under different voltage rise times and fall times are compared to reveal the influence mechanism of rise time and fall time on the surface discharge under positive repetitive square voltage.

Active Gate Driver and Management of the Switching Speed of GaN Transistors during Turn-On and Turn-Off

The paper investigates the management of drain voltage and current slew rates (i.e., dv/dt and di/dt) of high-speed GaN-based power switches during the transitions. An active gate voltage control (AGVC) is considered for improving the safe operation of a switching cell. In an application of open-loop AGVC, the switching speeds vary significantly with the operating point of the GaN HEMT on either or both current and temperature. A closed-loop AGVC is proposed to operate the switches at a constant speed over different operating points. In order to evaluate the reduction in the electromagnetic disturbances, the common mode currents in the system were compared using the active and a standard gate voltage control (SGVC). The closed-loop analysis carried out in this paper has shown that discrete component-based design can introduce limitations to fully resolve the problem of high switching speeds. To ensure effective control of the switching operations, a response time fewer than 10 ns is required for this uncomplex closed-loop technique despite an increase in switching losses.

Full Custom Design of an Arbitrary Waveform Gate Driver With 10-GHz Waypoint Rates for GaN FETs

Active gate driving of power devices seeks to shape switching trajectories via the gate, for example, to reduce EMI without degrading efficiency. To this end, driver ICs with integrated arbitrary waveform generators have been used to achieve complex gate signals. This article describes, for the first time, the implementation details of a digitally programmable arbitrary waveform gate driver capable of a 10-GHz waypoint rate, including comprehensive design considerations for critical high-speed subsystems that codify the tradeoff in flexibility, speed, and area. The design, which is taped out in a 180-nm high-voltage CMOS process, utilizes buffers that switch up to ten times in a single clock cycle to overcome the limited achievable clock speed of high-voltage silicon integrated circuits and a fully digital architecture to provide robustness under high slew rates of the ground rail. The driver IC has networks of 100-ps delay elements that are configured prior to a switching transient, to selectively control an array of fast, parallel-connected drivers with different output impedances. Key to the high timing resolution are high-speed asynchronous circuits for memory readout, output buffering, and pulse generation. The driver IC is experimentally evaluated to have a 100-ps resolution and to operate reliably in a 400-V gallium nitride (GaN) bridge leg, under ground-rail voltage slew rates peaking at over 100 V/ns. Design rules are provided to obtain an architecture with the least area for a given set of timing and impedance resolution requirements. The reported design methods enable complex driving waveforms to be applied during nanosecond-scale transients of GaN power devices and demonstrate how digitally programmable active gate drivers for GaN power FETs can be designed to meet a given set of application requirements.

Analytical Calculation of the Residual ZVS Losses of TCM-Operated Single-Phase PFC Rectifiers

Triangular-current-mode (TCM) modulation guarantees zero-voltage-switching across the mains cycle in AC-DC power converters, eliminating hard-switching with a minor ${\approx} {30}{\%}$ penalty in conduction losses over the conventional continuous current mode (CCM) modulation scheme. TCM-operated converters, however, include a wide variation in both switching frequency and switched current across the mains cycle, complicating an analytical description of the key operating parameters to date. In this work, we derive an analytical description for the semiconductor bridge-leg losses in a TCM AC-DC converter, including the rms current and/or conduction losses, switching frequency, and switching losses. For SiC mosfet s, we introduce a new loss model for switching losses under zero-voltage-switching, which we call “residual ZVS losses”. These losses include the constant $C_\text{oss}$ losses found in previous literature but must also add, we find, turn-off losses that occur at high switched currents. The existence and modeling of these turn-off losses, which are due to currents flowing through the Miller capacitance and raise the inner gate source voltage to the threshold level and accordingly limit the voltage slew rate, are validated on the IMZA65R027M1H 650V SiC mosfet . The complete loss model – and the promise of TCM for high power density and high efficiency – is validated on a 2.2 kW hardware bridge-leg demonstrator, which achieves a peak 99.6 $\%$ semiconductor efficiency at full load. The proposed, fully-analytical model predicts bridge-leg losses with only 12 $\%$ deviation at the nominal load, accurately including residual ZVS losses across load, modulation index, and external gate resistance.

Isolated Ultrafast Gate Driver with Variable Duty Cycle for Pulse and VHF Power Electronics

Ultrafast and isolated gate drivers advance the development of pulse and very high frequency power electronics for applications that include LiDAR, space systems, miniaturized hardware, and testing of emerging ultrafast devices. The isolated ultrafast gate driver in this letter achieves a gate voltage slew rate above 12 GV/s with rise and fall times below 260 ps with the proper choice of components. Magnetic isolation provides transient immunity and positive feedback enables dynamic dc restoration to allow arbitrarily long on - and off -times and preserve variable duty cycles. With the isolated ultrafast gate driver, an EPC 2038 GaN FET achieves a drain voltage slew rate of over 37 GV/s when hard-switching and improves total efficiency by 8% (including gating loss) with a careful choice of logic inverters in a symmetric 100 MHz current-mode class D (CMCD) wireless power transfer system. The ultrafast gate driver with isolation and positive feedback was implemented with a commercial radio frequency signal transformer and discrete logic inverters and validated in a hard-switching double pulse test, a narrow pulse test repeating at 165 MHz, and a 100 MHz soft-switching CMCD resonant converter.