Abstract
Active gate driving of power devices seeks to shape switching trajectories via the gate, for example, to reduce EMI without degrading efficiency. To this end, driver ICs with integrated arbitrary waveform generators have been used to achieve complex gate signals. This article describes, for the first time, the implementation details of a digitally programmable arbitrary waveform gate driver capable of a 10-GHz waypoint rate, including comprehensive design considerations for critical high-speed subsystems that codify the tradeoff in flexibility, speed, and area. The design, which is taped out in a 180-nm high-voltage CMOS process, utilizes buffers that switch up to ten times in a single clock cycle to overcome the limited achievable clock speed of high-voltage silicon integrated circuits and a fully digital architecture to provide robustness under high slew rates of the ground rail. The driver IC has networks of 100-ps delay elements that are configured prior to a switching transient, to selectively control an array of fast, parallel-connected drivers with different output impedances. Key to the high timing resolution are high-speed asynchronous circuits for memory readout, output buffering, and pulse generation. The driver IC is experimentally evaluated to have a 100-ps resolution and to operate reliably in a 400-V gallium nitride (GaN) bridge leg, under ground-rail voltage slew rates peaking at over 100 V/ns. Design rules are provided to obtain an architecture with the least area for a given set of timing and impedance resolution requirements. The reported design methods enable complex driving waveforms to be applied during nanosecond-scale transients of GaN power devices and demonstrate how digitally programmable active gate drivers for GaN power FETs can be designed to meet a given set of application requirements.
Highlights
In hard-switched power converters, fast power-circuit transients are targeted in order to reduce switching loss, but faster transients tend to increase undesirable circuit behaviours such as overshoots, ringing, and EMI
During the switching transients of each power device, these active gate drivers modulate their output impedance according to a sequence of pre-programmed waypoints, see Fig. 1
A sub-GHz waypoint rate results in limited waveform shaping capability, but rates greater than 1 GHz are beyond achievable clock speeds in high-voltage CMOS silicon processes that are typically used for gate drivers
Summary
In hard-switched power converters, fast power-circuit transients are targeted in order to reduce switching loss, but faster transients tend to increase undesirable circuit behaviours such as overshoots, ringing, and EMI. For GaN-based circuits where power-circuit transients are measured in units of nanoseconds, a key specification of these drivers is the rate at which waypoints are processed and output. The main challenge is to achieve sufficient analogue bandwidth, to make the power waveforms follow a reference waveform with nanosecond transient features, whilst maintaining an acceptable power consumption Such closedloop techniques are beginning to be developed for GaN [13], achieving the required speeds is a challenge, as some of the unwanted features in switching transients (such as the temporary inductive drop in drain-source voltage during turnon) have frequency components upwards of 10s of GHz [14]. The top-level architecture, circuit designs, trade-off analyses and experimental results presented in this paper demonstrate how digitally-programmable active gate drivers for GaN power FETs can be designed to meet a given set of application requirements.
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