Reference Voltage Generator Research Articles

Super-twisting MPPT control for grid-connected PV/battery system using higher order sliding mode observer

In recent times, photovoltaic (PV) power generation has been growing due to increase in energy demand. In grid-connected mode, achieving maximum power (MP) from the PV array is difficult by using conventional techniques due to various reasons like low tracking efficiency, stability issues, etc. This motivates the design of an appropriate control strategy to obtain the maximum power point tracking (MPPT) to harvest MP from the PV array. This paper proposes a combined higher order sliding mode observer (HOSMO)–super-twisting control (STC) for a grid-connected scenario. A perturb and observe (P &O) technique is employed to generate reference voltage, and a HOSMO is proposed to drive the STC by estimating the inductor current of the PV boost converter. The proposed controller performance is evaluated based on response time across various scenarios, including generation changes, dynamic faults, islanding and resynchronization, and load variations in comparison to other existing controllers. These microgrid test cases have been thoroughly simulated, and their effectiveness has been validated in real-time using OPAL-RT (OP4510).

Simulation and Analysis of Dynamic Voltage Restorer with PI Controller under Different Fault Condition

Abstract: This document gives formatting instructions for authors preparing papers for publication in the Proceedings of an IEEE conference. The authors must follow the instructions given in the document for the papers to be published. You can use this document as both an instruction set and as a template into which you can type your own text. The demand for quality power has become a challenging issue for industrial area and consumers. Among them voltage unbalance is considered as the major affecting problem leads to degradation in performance of electrical equipments. FACTS devices used for compensation are the best method to overcome such problem. Among them DVR considered the most efficient and cost effective. In a control system of the DVR main consideration includes: detection of the start and finish of the sag, voltage reference generation, transient and steady-state control of the injected voltage, and protection of the system. In this work, the simulation model of nonlinear load connected power distribution system with Dynamic voltage Restorer controlled by PI Controller has been developed using Matlab/Simulink. In this case we simulate three fault likewise: Three-line to ground fault, Double-line to ground fault and Single-line to ground fault with two different PI controller to study the THD.

Decentralized Virtual Impedance Control for Power Sharing and Voltage Regulation in Islanded Mode with Minimized Circulating Current

In islanded operation, precise power sharing is an immensely critical challenge when there are different line impedance values among the different-rated inverters connected to the same electrical network. Issues in power sharing and voltage compensation at the point of common coupling, as well as the reverse circulating current between inverters, are problems in existing control strategies for parallel-connected inverters if mismatched line impedances are not addressed. Therefore, this study aims to develop an improved decentralized controller for good power sharing with voltage compensation using the predictive control scheme and circulating current minimization between the inverters’ current flow. The controller was developed based on adaptive virtual impedance (AVI) control, combined with finite control set–model predictive control (FCS-MPC). The AVI was used for the generation of reference voltage, which responded to the parameters from the virtual impedance loop control to be the input to the FCS-MPC for a faster tracking response and to have minimum tracking error for better pulse-width modulation generation in the space-vector form. As a result, the circulating current was maintained at below 5% and the inverters were able to share an equal power based on the load required. At the end, the performance of the AVI-based control scheme was compared with those of the conventional and static-virtual-impedance-based methods, which have also been tested in simulation using MATLAB/Simulink software 2021a version. The comparison results show that the AVI FCS MPC give 5% error compared to SVI at 10% and conventional PI at 20%, in which AVI is able to minimize the circulating current when mismatch impedance is applied to the DGs.

A Quadrature Oscillator with a Frequency-Tuned Distributed RC Network Analysis

This paper introduces an innovative two-stage distributed RC oscillator design, enhancing the noise performance and frequency stability for compact electronic devices. This work significantly reduces the comparator noise and improves system reliability by implementing a novel approach to increase the signal transition slope, coupled with optimized resistor and capacitor configurations. The study employs a quadrature oscillator topology and a precise reference voltage generation method, effectively addressing the challenges of mismatch and noise performance. A 469.2 kHz quadrature oscillator with two-stage distributed RC is implemented with a 0.18 μm CMOS process, achieving a FoM of −160 dBc/Hz at 100 Hz with a stable −20 dB roll-off in the phase noise and an Allan deviation floor of less than 0.7 ppm.

Parallel Operation Strategy of Inverters Based on an Improved Adaptive Droop Control and Equivalent Input Disturbance Approach

The operation of parallel inverters in microgrids is an important way to expand system capacity, but there are problems of circulating current fluctuations and power sharing errors in parallel inverters’ operation. In this paper, a parallel operation strategy for inverters based on improved adaptive droop control and Equivalent Input Disturbance (EID) is proposed. Firstly, the model and control topology of parallel inverters are presented. Secondly, in order to solve the power sharing error caused by impedance difference and the voltage drop caused by virtual impedance, a reference voltage generator based on improved adaptive droop control is proposed. Then, considering the circulating current fluctuation as a disturbance, a voltage controller based on an equivalent input disturbance approach is proposed to reduce the disturbance. Finally, simulation in MATLAB/Simulink is carried out to verify the effectiveness of the parallel operation strategy.

A 9T-SRAM in-memory computing macro for Boolean logic and multiply-and-accumulate operations

Artificial intelligence algorithms play important roles in image classification to speech recognition, which contains enormous Boolean logic and multiplication operations. Traditional von Neumann architecture separates computing and storage units, which leads to “power walls” and “memory walls” problems. In-memory computing (IMC) is a promising method to solve these problems. In this work, we propose an IMC macro based on customed 9T-SRAM, which can be configured in memory, Boolean logic and multiply-and-accumulate (MAC) modes. The 9T-SRAM adopts read/write decoupled and a tail transistor structure, which enhances the read stability and reduces power consumption. With the bias rows, Boolean logic results are obtained from the differential voltages on two bitlines, reducing the peripheral circuit for reference voltage generation. Furthermore, the bias rows replace analog to digital converter (ADC) to binarize the MAC result, reducing the area overhead. In a 55 nm process, simulations manifest the 9T-SRAM shows enhanced read static noise margin, and the macro exhibits stable IMC operations and high energy-efficiency.

A Sub-1 ppm/°C dual-reference small-area bandgap reference comprising an enhanceable piecewise curvature compensation circuit

This paper presents a low-temperature coefficient (TC) dual-reference CMOS bandgap reference (BGR) for high-performance systems working under a wide temperature range. It consists of a correction approach to eliminate the high-order inaccuracy, in which an enhanceable curvature compensation circuit is adopted to extend the operating temperature range and generate reference voltages with sub-1 ppm/°C TC. In addition, a voltage level shifter (VLS) is used to generate the latter compensated reference voltage but no need for an additional compensation circuit. The proposed BGR designed in a 0.18-µm CMOS process has a simulated TC of 0.75 ppm/°C and 0.28 ppm/°C for the first and second reference outputs, respectively, over a wide temperature range of −50 °C to 130 °C. The proposed BGR occupies a 0.0079-mm2 silicon area. The overheads make the BGR appropriate to provide reference voltages in diverse chips with high-precision systems.

A Capacitive Computing-In-Memory Circuit With Low Input Loading SRAM Bitcell and Adjustable ADC Input Range

We present a 9T1C SRAM cell-based capacitive computing-in-memory circuit for neural network computation. The proposed design improves tolerance against process variation with a smaller cell area compared to previous capacitive SRAM CIM designs while inheriting the advantage of capacitive SRAM CIM hardware such as the linearity in multiply-accumulate (MAC) results and suppression of the static readout current. We also demonstrate a compact and low-power ADC for CIM readout, which improves the energy efficiency significantly. Finally, we demonstrate a programmable on-chip ADC reference voltage generator circuit for adjusting the ADC input range using bitcell replica arrays. The proposed circuit reduces the ADC bit-resolution requirement by considering the distribution of MAC results, and also helps to address the effect of the parasitic bitline capacitance. Measurement results show that a 128×128 macro fabricated in a 28 nm CMOS achieves 1519.5 TOPS/W at 0.7 V.

Fault Control Strategy of Grid‐Forming Converter Considering the Voltage Support of Faulty Phase

AbstractThe grid‐forming converter (GFC) is used to regulate the voltage and frequency of a local grid. However, due to the limited current capacity, the GFC must actively modify its control strategy when a serious external fault occurs, thus to avoid the possible damage caused by overcurrent. This paper proposes a novel voltage reference generation method for GFC based on the external equivalent impedance magnitude (EEIM), which has the following merits: (i) the faulty phase currents and the non‐faulty phase voltage can be controlled within their operational limits. (ii) The voltage reference unbalance factor (VRUF) of the GFC can be adjusted flexibly if necessary. Then, in order to achieve the optimal support effect for the faulty phase voltages, a two‐stage GFC fault control strategy is proposed in this paper. In the first stage, the fault type is judged by computing and comparing the EEIM of each phase. In the second stage, the voltage reference mode is determined according to the fault type, and the VRUF is adjusted to its optimum value through a search algorithm. Simulation results based on Matlab/Simulink verify the effectiveness of the proposed GFC fault control strategy in terms of current limiting and faulty phase voltage support. © 2023 Institute of Electrical Engineer of Japan and Wiley Periodicals LLC.

A 2941-TOPS/W Charge-Domain 10T SRAM Compute-in-Memory for Ternary Neural Network

In this paper, we present a 10T SRAM compute-in memory (CiM) macro to process the multiplication-accumulation (MAC) operations between ternary-inputs and binary-weights. In the proposed 10T SRAM bitcell, the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">charge-domain</i> analog computations are employed to improve the noise tolerance of bit-line (BL) signals where the MAC results are represented in CiM. Parallel processing of 3 different analog levels for ternary input activations is also performed in the proposed single 10T bitcell. To reduce the analog-to-digital converter (ADC) bit-resolutions without sacrificing deep neural network (DNN) accuracies, a confined-slope non-uniform integration (CS-NUI) ADC is proposed, which can provide layer-wise adaptive quantization for multiple different layers with different MAC distributions. In addition, by sharing the ADC reference voltage generator in every single column of SRAM array, the ADC area is effectively reduced with improved energy efficiencies of CiM. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$256\times64.10$</tex-math> </inline-formula> T SRAM CiM macro with the proposed charge-sharing scheme and CS-NUI ADCs has been implemented using 28nm CMOS process. The silicon measurement results show that the proposed CiM shows the accuracies of 98.66% and 88.48% with MNIST dataset on MLP, and CIFAR-10 dataset on VGGNet-7, respectively, with the energy efficiency of 2941-TOPS/W and the area efficiency of 59.584-TOPS/mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> .

Optimizing Large-Scale PV Systems with Machine Learning: A Neuro-Fuzzy MPPT Control for PSCs with Uncertainties

The article proposes a new approach to maximum power point tracking (MPPT) for photovoltaic (PV) systems operating under partial shading conditions (PSCs) that improves upon the limitations of traditional methods in identifying the global maximum power (GMP), resulting in reduced system efficiency. The proposed approach uses a two-stage MPPT method that employs machine learning (ML) and terminal sliding mode control (TSMC). In the first stage, a neuro fuzzy network (NFN) is used to improve the accuracy of the reference voltage generation for MPPT, while in the second stage, a TSMC is used to track the MPP voltage using a non-inverting DC—DC buck-boost converter. The proposed method has been validated through numerical simulations and experiments, demonstrating significant enhancements in MPPT performance even under challenging scenarios. A comprehensive comparison study was conducted with two traditional MPPT algorithms, PID and P&amp;O, which demonstrated the superiority of the proposed method in generating higher power and less control time. The proposed method generates the least power loss in both steady and dynamic states and exhibits an 8.2% higher average power and 60% less control time compared to traditional methods, indicating its superior performance. The proposed method was also found to perform well under real-world conditions and load variations, resulting in 56.1% less variability and only 2–3 W standard deviation at the GMPP.

180 nm FLASH ANALOG TO DIGITAL CONVERTOR

In this paper, Threshold Inverter Quantizer (TIQ) is a novel idea which can effectively replace the reference voltage generator, resistive/capacitive voltage divider network and array of differential comparators in a conventional flash Analog to Digital Converter (ADC) by an internal reference comparator array constructed of Complementary Metal Oxide Semiconductor (CMOS) inverters. The inverter threshold voltage serving as the reference voltage, this architecture claims large improvements in terms of silicon area, power consumption and operating speed. Perturbations due to sensitivity of the inverter threshold voltage to operating temperature/process variations pose impediments in such ADC designs and strongly demand a compensation scheme to such variations. This paper presents a TIQ based flash ADC, with inverter threshold voltage compensation. In this project 5 bit flash adc using TIQ Comparator is designed and simulated using TANNER EDA in 180nm technology. Key Words: flash, adc, tiq(threshold inverter quantization)

Fuzzy induced controller for optimal power quality improvement with PVA connected UPQC

Abstract The major power quality issues in grid are voltage fluctuations and harmonics. For better power quality of the power system during disturbances on the grid, the UPQC device is utilized to maintain voltage magnitude and reduced harmonics. At the DC link of UPQC along with the capacitor, a renewable PV source is connected which contributes in voltage compensation by the series VSC and harmonics compensation by the shunt VSC. For stable DC voltage generation from PV source a modified P&amp;O MPPT with DC reference is included controlling the boost converter connected to PV source. The controllers of VSCs are operated by feedback loop synchronized schematics with voltage reference generation in series VSC control and current reference generation in shunt VSC control. The shunt control is updated with hybrid Fuzzy-PI controller replacing the traditional PI controller further improving the power quality of the grid. The hybrid Fuzzy-PI varies the K p and K i gains as per the error generated by the DC voltage comparison concerning 25 rule-base for each gain. A comparative performance analysis is done with both the controllers in the shunt converter and the results are generated using MATLAB Simulink software.

Modeling of a Wind Power System Using the Genetic Algorithm Based on a Doubly Fed Induction Generator for the Supply of Power to the Electrical Grid

This paper is interested in studying a system consisting of a wind turbine operating at variable wind speeds, and a two-feed asynchronous machine (DFIG) connected to the grid by a stator and fed by a transducer at the side of the rotor. The conductors are separately controlled for active and reactive power flow between the stator (DFIG) and the grid. The proposed controllers generate reference voltages for the rotor to ensure that the active and reactive power reaches the required reference values, to ensure effective tracking of the optimum operating point and to obtain the maximum electrical power output. Dynamic analysis of the system is performed under variable wind speeds. This analysis is based on active and reactive energy control. The new work in this paper is to introduce theories of genetic algorithms into the control strategy used in the switching chain of wind turbines in order to improve performance and efficiency. Simulation results applied to genetic algorithms give greater efficiency, impressive results, and stability to wind turbine systems are compared to classic PI regulators. Then, artificial intelligent controls, such as genetic algorithms control, are applied. Results obtained in the Matlab/Simulink environment show the efficiency of this proposed unit.

Model Predictive Control of Transformerless Series Custom Power Device for Voltage Quality Improvement

A single-phase series custom power device (Se-CPD), based on model predictive control (MPC), is presented in this paper to compensate for erratic supply voltage conditions such as voltage sag, swell, and harmonics. The control strategy for Se-CPD encapsulates the generation of reference voltage and optimal switching signals for the voltage source inverter (VSI) of the Se-CPD. The reference voltage extraction from the distorted point of common coupling (PCC) voltage is synthesized using a second-order generalized integrator (SOGI) without any phase delay, unlike the case that uses a low-pass filter (LPF). An MPC realizes the generation of optimal switching signals for Se-CPD with its intuitive and straightforward implementation, without any modulation stage, and considers the converter’s switching characteristics in the MPC algorithm itself. The simulation results, using MATLAB/Simulink and the real-time simulation results using the OPAL-RT OP4510 real-time simulator, are presented to validate the SOGI-MPC’s effectiveness for voltage quality improvement.

An FCS-MPC Strategy for Series APF Based on Deadbeat Direct Compensation

Aiming at the delay caused by the phase-locked loop (PLL) and harmonic detection in the traditional control of a series active power filter (SAPF), a deadbeat direct control (DBDC)-based finite control set model predictive control (FCS-MPC) strategy for the SAPF is proposed in this work. Firstly, a reference voltage generation mechanism based on direct control is established, which avoids the delay in harmonic detection, thus improving the dynamic response performance of the system. Secondly, the reference current generation mechanism suitable for the SAPF is derived and established using the deadbeat control (DBC) in the αβ coordinate system, based on which the FCS-MPC system is constructed. It eliminates the complex coordinate transformation and PLL and effectively compensates for the full-frequency harmonic voltage. Finally, the proposed control strategy is verified by a simulation and an experiment. The results suggest that the proposed control strategy can effectively compensate for the load voltage and suppress harmonic distortion for the temporary swell and sag of the grid voltage, sudden load changes, and harmonic distortion conditions.

Simple and Fast Voltage Disturbance Detection and Voltage Reference Generation Approach for Dynamic Voltage Restorer (DVR) to Compensate Unbalanced Voltage Sag and Swell in Three-Phase System: Simulation and Experimental Testing

The dynamic voltage restorer (DVR) is an important device for coping with voltage sag, swell, and unbalance. However, it is a real-time mechanism and must operate as quickly as possible to protect the sensitive and critical load from supply-side voltage anomalies. Hence, fast detection of voltage disturbances and reference voltage generation is essential for the DVR. This paper proposes a simple and fast voltage disturbance detection approach based on a simple three-phase phasor diagram which is easy to implement. The controller employed for the DVR uses a sliding mode control, making the entire system robust and insensitive to system parameter variations. Three different scenarios are simulated according to arbitrarily imposed supply conditions, verified in laboratory tests using the DSP R&amp;D controller board. The results demonstrate a simpler, faster voltage-anomaly detection process which is easier for implementation compared to the other methods in the literature. The best and worst detection times (DTs) of the proposed approach are 1 and 4 ms, respectively. It yields a rapid response, accurate compensation, and robustness in restoring the load voltage to its nominal value within two cycles.

An Ultra Low-Power Programmable Voltage Reference for Power-Constrained Electronic Systems

This paper proposes a novel architecture for the generation of a programmable voltage reference: the background-calibrated (BC)-PVR. Our mixed-signal architecture periodically calibrates a static ultra low-power voltage reference generator, from an accurate bandgap reference. The portion of the chip used for the calibration can be powered down with a programmable duty-cycle. The system aims to fully exploit the small temperature derivative vs time <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$D_{T}$ </tex-math></inline-formula> of several application domains to minimize the average current consumption. The BC-PVR has been designed and implemented in TSMC 55-nm CMOS technology, and it achieves the largest reported programming reference output range [0.42 - 2.52] V, over the temperature range [−20, 85] °C. The duty-cycle mode allows nanoampere current consumption, and the large design flexibility permits to optimize the system performance for the specific application. These features make the BC-PVR very well-suited for power-constrained electronic systems.

DC-AC Converter with Dynamic Voltage Restoring Ability Based on Self-Regulated Phase Estimator-DQ Algorithm: Practical Modeling and Performance Evaluation

A self-regulated phase estimator (SRPE)-based DQ algorithm for a DC-AC converter with dynamic voltage restoring (DVR) ability is presented in this paper. When compared to the conventional phase-locked loop (PLL), the provided controller can significantly reduce phase distortions and low-order harmonics from the load voltage while attaining quicker dynamic response. Furthermore, the fundamental attribute of the load voltage allows the integrated DC-AC converter to operate at a consistent frequency eliminating frequency oscillations. The SRPE is utilized primarily in the DQ control theory as the reference voltage generator which can compensate for the grid voltage. SRPE has good band-pass filtering properties and a mathematically simple structure that can thoroughly attenuate voltage imbalance and has quick dynamic response. The SRPE has been made to be frequency-adaptive using a damping factor and robust grid frequency estimation. The SRPE can maintain the fundamental frequency at 50 Hz and keep the total harmonic distortions (THD) within the 5% limit even during grid disruptions. The DC-AC converter and SRPE-DQ’s stability are thoroughly examined. The experiment is carried out to show the efficacy of the suggested complete control system. There are also comparative simulation studies to show the benefits of the suggested technique. The results reveal that the suggested approach can immediately identify and correct for any grid voltage imbalance while also assisting in maintaining the constant voltage at the load side despite voltage sag/swell and distortions.

Artificial intelligence based nonlinear control of hybrid DC microgrid for dynamic stability and bidirectional power flow

Conventional power generation resources are depleting rapidly and world power sector has been moving towards renewable energy sources (RESs). In this paper nonlinear control for renewable energy and hybrid energy storage system (HESS) based DC microgrid (DCMG) has been presented. PV and wind energy being the renewable sources whereas fuel cell, battery and ultracapacitor constitute the HESS. The global mathematical model of the said system has been presented. Datasets of varying solar irradiance and temperature have been trained by Artificial Neural Network for the reference voltage generation of PV. Integral terminal sliding mode controller (ITSMC) has been proposed for the output DC bus voltage regulation. Lyapunov stability criterion has ensured the overall stability of the system. A comparison of ITSMC with SMC and Lyapunov redesign controller has also been presented. Grid connected battery electric vehicle charger with grid to vehicle (G2V) and vehicle to grid modes (V2G) has been presented being an application of DCMG. The proposed system has been validated by using MATLAB/Simulink (2020b). Moreover, the hardware in loop setup has been used to observe the real time applicability of the proposed controller.