Level Shifter Research Articles

Surface-Induced Electronic and Vibrational Level Shifting of [Fe(py)2bpym(NCS)2] on Al(100).

It is essential that one understands how the surface degrees of freedom influence molecular spin switching to successfully integrate spin crossover (SCO) molecules into devices. This study uses density functional theory calculations to investigate how spin state energetics and molecular vibrations change in a Fe(II) SCO compound named [Fe(py)2bpym(NCS)2] when deposited on an Al(100) surface. The calculations consider an environment-dependent U to assess the local Coulomb correlation of 3d electrons. The results show that the adsorption configurations heavily affect the spin state splitting, which increases by 10-40 kJmol-1 on the surface, and this is detrimental to spin conversion. This effect is due to the surface binding energy variation across the spin transition. The preference for the low-spin state originates partly from the strong correlation effect. Furthermore, the surface environment constrains the vibrational entropy difference, which decreases by 8-17 Jmol-1K-1 (at 300 K) and leads to higher critical temperatures. These results suggest that the electronic energy splitting and vibrational level shifting are suitable features for characterizing the spin transition process on surfaces, and they can provide access to high-throughput screening of spin crossover devices.

Development of compact voltage level-up shifter for nano-second delay system-on-chip applications

The Level Shifter is made with two inverters and a Wilson current mirror to use less energy. In order to reduce the amount of leaking power, this study suggests using a combination of super-cut-off draw-down and stacked pull-up networks. The design also incorporates multi-threshold complementary-metal-oxide-semiconductor (MTCMOS) technology, which, consists of sleeper transistors that are able to boosts performance without increasing either power usage or size. The designed device can be used to shift voltage in between 0.4 V and 1.2 V. To suit nano-scale uses, the circuit’s operating range and performance factors (such as power, latency, and area) were fine-tuned. According to the results, ‘level-up’ transitions typically consume 148.6nW of active power and have an average delay of 1.19 ns at 1 MHz transmission rates. The post-layout model indicated that the recommended plan would need 9.47 μm2 of floor space. The results are analyzed in Cadence Virtuoso using 45 nm techniques.

Design of GPIO Transmitter

Abstract: This paper presents a comprehensive design approach for a versatile 1.8V GPIO transmitter tailored for a 5pf load capacitance. The work introduces a novel design that accommodates 1.8V IO supply, enhancing the flexibility and compatibility of the GPIO transmitter. The GPIO consists of a level shifter and a driver. A level up shifter is used along with a driver capable of driving the signals without any data loss. The work embarks on the objective of designing a robust GPIO transmitter by utilizing a combination of level shifting and driver circuitry. The methodology encompasses meticulous simulation-driven design, encompassing a 45nm technology node and the Cadence Virtuoso platform. The design incorporates a level shifter that elevates input data from a core domain operating at 0.8V to IO levels of 1.8V , ensuring seamless communication across various voltage domains. The driver circuit, implemented with progressive sizing, effectively drives the substantial load capacitance of 5pF, maintaining the integrity of input data. Through detailed analysis, the architecture ensures compliance with the demanding specifications of Intel Max 10 FPGA. Simulation results exhibit the efficacy of the proposed design. The level shifter successfully transforms an incoming 0.8V data signal to 1.79V , aligning with the 1.8V IO requirements. The driver also drives the same signal out with a load of 5pf. The level shifter and driver is combined to check for the working of transmitter, with input at 0.8V and the signal is obtained at the expected voltage level at the output of driver

An Electromagnetic Interference Immune PAM-4 Transceiver System

This article presents the design of a pulse amplitude modulation (PAM-4) transceiver that supports high-speed wireline communication in the presence of electromagnetic interference (EMI). The proposed PAM-4 transceiver uses an input level shifter (ILS) and a modified electrostatic discharge (ESD)-protection circuit to reduce the effects of EMI at the transmitter. In order to overcome the effects of EMI at the receiver, the front end is designed with an enhanced input common-mode range. The transverse electromagnetic (TEM) cell method, as provided in the IEC 62132-2 standard, is followed to experimentally verify the radiated EMI-immunity of the proposed PAM-4 transceiver system over its traditional counterpart. For proof of concept, the proposed EMI-immune PAM-4 transceiver and the traditional PAM-4 transceiver circuits are implemented using the 130-nm BiCMOS process. The proposed transceiver operates at a data rate of 6.5 Gbps while maintaining an eye-opening of 70 mV for each bit in the presence of EMI, meeting the requirement of the IEEE 802.3 bs standard. The proposed PAM-4 transceiver withstands a wide range of EMI frequencies that span from 150 kHz to 2 GHz with an EMI power of 0–20 dBm.

A Digitally-Controlled Integrated Circuit Solution for Tinnitus Treatment with Charge Balancing.

An integrated circuit specified for tinnitus treatment is described. This chip, realized using a 0.18um BCD high-voltage CMOS process, is capable of generating current stimulus with any wave shape directly into the inner-ear tissue without the need for off-chip control circuitry. Used as part of a multi-chip module that can be implanted into the inner ear, this core chip contains an 8-bit digital-to-analog converter, an amplitude control block, a novel high-voltage drive and charge balance circuit, a high-voltage level shifter, an SRAM, a ROM, and an on-chip central control unit. The chip can achieve ±0.1 mV charge-balance precision.

High Speed and Low Leakage Power Voltage Level Shifter using Regulated Cross-Coupled Network

This concise presents a power efficient level shifter using regulated cross-coupled network with split inverter. With the use of regulated cross-coupled network, power dissipation of the pull-up region drastically decreases. Level shifters convert the voltage levels which are below the threshold voltage to the acceptable voltage levels by decreasing the transistor size. A Split inverter is used at the output to decrease the short circuit current. Modified Split inverter along with the load capacitor at the output is used to increase the speed and to decrease the power consumption. This LS can save 31% power compared to other techniques. The proposed level shifter works effectively at high speed and consumes less power. For simulation, LT spice tool of 50 nm technology and 90 nm technology is used.

A 38.5-fJ 14.4-ns Robust and Efficient Subthreshold-to-Suprathreshold Voltage-Level Shifter Comprising Logic Mismatch-Activated Current Control Circuit

This brief presents a robust and energy-efficient voltage level shifter (VLS) for wide-range conversion from the subthreshold to the suprathreshold regime. The proposed VLS contains a new logic mismatch detection circuit to address the exist contention current of the conversion stage. A power reducer circuit is introduced to increase the drivability of pull-up and pulldown devices in linear and cut-off regions and further energyconsuming improvement. The proposed VLS is simulated using a 0.18-lm process, the minimal convertible voltage is 0.2 V (deep subthreshold region) for the input signal. Post-layout simulation considering process voltage temperature (PVT) variations proves the proposed VLS outperforms previous designs in several aspects. The results report the consuming energy of 38.5 fJ per transition, a static power of 73.4 pW, and a delay of 14.4 ns when converting range is 0.4 V to 1.8 V. The proposed VLS occupies a 59.98-lm2 silicon area.

Bio-Hash Secured Hardware e-Health Record System.

Dual securing strategy for all-hardware e-Health Record System is designed and developed for improved security and reduced Hardware Execution Time (HET). A compact novel Hashed Minutiae Random Fusion (HMRF) logic enables to achieve high irreversibility and increased non-reconstruction capability of the bio-template based Bio-Hash key. AES encryption of the patient's health data during Write mode and decryption during View mode are seamlessly performed through the lively generated key, yielding low HET through optimized slack. On the other hand, biometric controlled key retrieval during Read only mode for a single user access is performed on the pre-scrambled Bio-Hash key, to enable bypassed decryption (direct) of the Patient's health data for self-review. The proposed pseudo cascaded SHA-3 (Secured Hash Algorithm) architecture being the first stage in HMRF, hashes the biometric minutiae of both Patient (P) and Medical Practitioner (MP) with low Latency. Thus, facilitating in further lowering of the HET by reducing the clock count by one. The subsequent Random Compression Logic (RCL) skims the hashed value from 512 to 128 bits along with the help of priority compression logic (PCL) to achieve reduced bits handling thereby lowering the Power budget. Four fusion modes are leveraged to achieve better randomization and non-recoverability. Implementation of this HMRF logic on Virtex-7 (V7) FPGA device has yielded low Area of 4191 slices. Lesser Area of 11.6% is observed for this HMRF module compared to the reported design, excluding level shifter and PCL. Further, low HETs of 8.2/8.3/8.0 ns during Write/View/Read only modes respectively are being noticed. The dynamic Power dissipated for the three modes of operations are found to be 1.418/1.420/0.676 watts respectively.

A level shifter for high-side GaN drivers with enhanced dV/dt immunity and speed

—In this paper, a level shifter with high dV/dt immunity and high speed is presented for GaN drivers. During dV/dt transitions of floating power supply, a resistor-based decoupling technique (RDT) is applied for the level shifter to completely eliminates the interference of dV/dt-induced noise on the output logic. A cross-controlled noise blanker (CCNB) is also added to further improve the reliability of output logic. The dV/dt immunity of the level shifter is significantly improved. Moreover, a short pulse charging circuit helps speed up response speed during level shifting. This circuit has been fabricated in a 0.35 μm 100 V HV CMOS process and occupies an active chip area of 0.055 mm2. Experimental results confirm that the proposed level shifter works at 5 MHz, achieving 80V/ns dV/dt immunity with a small figure of merit (0.057ns/(μm⋅V)).

Perancangan dan Pembuatan Data Acquisition Device Sebagai Sistem Akuisisi Data untuk Kendali Mobil Formula Student

Data Acquisition Device (DAQ) is an electronic component used in formula student vehicles. To optimize the performance of the formula student vehicle and its driver, it is necessary to analyze and monitor the data acquisition system. Parameters acquired on the car include the position of the brake pedal/throttole and wheel speed.DAQ system has 5 input channels namely 3 analog input pins and 2 digital input pins, and 3 output channels, which is the controller pin, fault pin, and brake light pin. The DAQ system in this research is designed and made using Teensy 3.6, a signal conditioning circuit consisting of an RC low pass filter, voltage follower, non-inverting amplifier, and logic level shifter. DAQ system uses CANBUS to read and process sensor data. DAQ system can acquire data from the KTC Linear Motion Position sensor PZ-12-A-50P with an accuracy value of 99,91%; Hall-effect Rotary Position sensor RTY120LVNAX with an accuracy value of 99,94% for both the first and second sensors; and Proximity sensor LJ12A3-4-Z/BX with an accuracy value of 99,58% for the first sensor and 99,46% for the second sensor. DAQ is able to run controller signal processing, detect faults, and activate brake light signal according to FSAE rules.

Class AB Voltage Follower and Low-Voltage Current Mirror with Very High Figures of Merit Based on the Flipped Voltage Follower

The application of the flipped voltage follower to implement two high-performance circuits is presented: (1) The first is a class AB cascode flipped voltage follower that shows an improved slew rate and an improved bandwidth by very large factors and that has a higher output range than the conventional flipped voltage follower. It has a small signal figure of merit FOMSS = 46 MHz pF/µW and a current efficiency figure of merit FOMCE = 118. This is achieved by just introducing an additional output current sourcing PMOS transistor (P-channel Metal Oxide Semiconductor Field Effect Transistor) that provides dynamic output current enhancement and increases the quiescent power dissipation by less than 10%. (2) The other is a high-performance low-voltage current mirror with a nominal gain accuracy better than 0.01%, 0.212 Ω input resistance, 112 GΩ output resistance, 1 V supply voltage requirements, 0.15 V input, and 0.2 V output compliance voltages. These characteristics are achieved by utilizing two auxiliary amplifiers and a level shifter that increase the power dissipation just moderately. Post-layout simulations verify the performance of the circuits in a commercial 180 nm CMOS (Complementary Metal Oxide Semiconductor) technology.

CARAT – A reliability analysis framework for BTI-HCD aging in circuits

Circuit Aging Reliability Analysis Tool (CARAT), a framework that calculates random activity (frequency and duty) aware degradation of FETs to simulate circuit aging under real operating workloads is proposed. Bias Temperature Instability (BTI) and Hot Carrier Degradation (HCD) induced degradation of FETs is calculated in a cycle-by-cycle manner based on actual terminal waveforms grabbed from SPICE. Framework capability is demonstrated by using Level Shifter (LS) under random data-path activity, and Ring Oscillator (RO) under Dynamic Voltage Frequency Scaling (DVFS) conditions. The risk associated with the standard blanket approach is discussed.

Design Of Voltage Level Shifter Using Regulated Cross Coupled Pull Up Networks

Level shifter plays an vital role in multiple supply voltage techniques which creates a path between processors, sensors or broads of different voltage levels, it converts the input logic levels or voltages below the VTH of the transistor to the higher acceptable levels depending upon the system requirements. So, it is necessary to design a level shifter circuit which provides high performance. Power consumption and delay are the key features which determines the performance of a level shifter. This project mainly focuses on designing the level shifter using regulated cross coupled pull up network which helps in utilizing less power and enhancing the speed of the circuit. The work carried out is the mini-project that is a part & parcel of the curriculum in the 2nd semester.

A Comprehensive Study on the Design Methodology of Level Shifter Circuits

The level shifter (LS) circuit has become an indispensable circuit component in both analog and digital systems. In the past decades, there has been an exponential increase in the academic publications for the LS circuits to improve their performances and their applications. Therefore, this review paper provides a comprehensive study of the LS circuit, ranging from circuit topologies and various design methodologies such as sizing methodology, layout design methodology, circuit evaluation methodology, and testing methodology. Finally, we evaluate the state-of-the-art LS circuits and present their performance metrics.

Ultra-Low-Power Low-Input-Voltage Charge Pump for Micro-Energy Harvesting Applications

A subthreshold input voltage charge pump based on the well-known cross-coupled voltage doubler and using boosted gate voltages for the transfer switches is presented. A level shifter and some inverters, including a novel inverter architecture proposed in this work and referred to as negative low-state voltage inverter, are used to generate the clock signals for the switching transistors with the purpose of significantly improving their drive capability. A complete analysis of the proposed charge pump is provided to highlight the advantages of the implemented structure, revealing the power efficiency improvement when the input voltage is below the threshold voltage of the transistors. An extensive experimental characterization of silicon prototypes in 180 nm CMOS technology was carried out, showing that the proposed scheme is able to pump charge from an input voltage as low as 110 mV. The experimental peak efficiency remains above 70% for input voltages between 180 mV and 400 mV and input power levels from 45 nW to 25 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> , which are appropriate for different miniaturized transducers implementable on chip.

BIST-Supported Cryogenic Write Trimming With In-MRAM Computing Case Study

In the processor-memory separated von- Neumann computation paradigm, the “memory-wall” effect becomes critical due to large access latency and tremendous amount of data movement. In this work, we pursue cryogenic temperature based memory design and focus on spin-transfer-torque magnetoresistive random access memory (STT-MRAM) at 77-Kelvin (achieved with low-cost liquid nitrogen). Cryogenic compact model and its related cryogenic bit-cell are investigated, based on 77 K experiment data of magnetic tunnel junction (MTJ) and CMOS transistor. Compared with the simulated room temperature results, 70% reduction of sensing latency can be obtained at 0.7 V supply voltage, whereas writing latency and yield performance are significantly degraded. In order to overcome the above drawbacks, a novel joint trimming system is proposed including a build-in- self-test (BIST) block and a string of multi-stage level shifters (LS). A case study is executed with in-MRAM computing (IMC). Results show that cryogenic IMC with write trimming provides performance improvements of 33% on average, and concurrently reduces memory energy consumption by 70% on average. The proposed 77 K cryogenic design method can be further applied to other energy constrained applications.

Temperature-Driven Twin Structure Formation and Electronic Structure of Epitaxially Grown Mg3Sb2 Films on Mismatched Substrates.

Mg3Sb2-based compounds are one type of important room-temperature thermoelectric materials and the appropriate candidate of type-II nodal line semimetals. In Mg3Sb2-based films, compelling research topics such as dimensionality reduction and topological states rely on the controllable preparation of films with high crystallinity, which remains a big challenge. In this work, high quality Mg3Sb2 films are successfully grown on mismatched substrates of sapphire (000l), while the temperature-driven twin structure evolution and characteristics of the electronic structure are revealed in the as-grown Mg3Sb2 films by in situ and ex situ measurements. The transition of layer-to-island growth of Mg3Sb2 films is kinetically controlled by increasing the substrate temperature (Tsub), which is accompanied with the rational manipulation of twin structure and epitaxial strains. Twin-free structure could be acquired in the Mg3Sb2 film grown at a low Tsub of 573 K, while the formation of twin structure is significantly promoted by elevating the Tsub and annealing, in close relation to the processes of strain relaxation and enhanced mass transfer. Measurements of scanning tunneling spectroscopy (STS) and angle-resolved photoemission spectroscopy (ARPES) elucidate the intrinsic p-type conduction of Mg3Sb2 films and a bulk band gap of ~0.89 eV, and a prominent Fermi level downshift of ~0.2 eV could be achieved by controlling the film growth parameters. As elucidated in this work, the effective manipulation of the epitaxial strains, twin structure and Fermi level is instructive and beneficial for the further exploration and optimization of thermoelectric and topological properties of Mg3Sb2-based films.

An improved three phase cascaded multilevel inverter for maximum power point tracking application

A Three Phase Cascaded Multilevel (21 level) Inverter (3PMLI) is a superior alternative to medium-voltage inverter with intrinsic component redundancy. The 3PMLI achieves high quality input current and output voltage through a series connection of single-phase inverters. In case of applications like elevators, downhill conveyors and energy plants, regenerative issue is considered maximal due to bidirectional power flow. Hence, a 3PMLI fails in providing the required regenerative operation. In this paper, the Grey Wolf Optimisation - Fuzzy Logic Controller (GWO-FLC) with PI controller is used to control the Maximum Power Point (MPP) tracking of the MPPT. This method uses a GWO-FLC is designed to tune the membership function of FLC. The GWO-FLC with PI controller produces reference waveform for the level shifting (LS) method, which generates commutation signals for the boost converter. LS used in the study is Multicarrier Level Shifting - Pulse Width Modulation (MCLS-PWM) that generates the commutation signals for boost converter. A 21 levelled 3PMLI is used with a regenerative topology that increases the applicability of MLI. The regenerative 3PMLI is used to drive the Photo-Voltaic(PV)Maximum Power Point Tracking (MPPT) application. The mathematical modelling of PV MPPT application is carried out with Simulink. The coding is developed in very high-speed description language (VHDL) and implemented on Xilinx SPARTAN-III 3AN-XC3S400-FPGA processor. The proposed strategy is compared with existing fuzzy based Genetic Algorithm and GWO to prove its effectiveness. An extensive experimental analysis of the proposed technique takes place on benchmark datasets and the resultant outcomes are investigated with respect to distinct measures. The simulation results highlighted the enhanced performance of the proposed technique compared to existing techniques.

A 72-dB SNDR 130-MS/s 0.8-mW Pipelined-SAR ADC Using a Distributed Averaging Correlated Level Shifting Ring Amplifier

This article presents a 14-b 130-MS/s two-stage pipelined-SAR analog-to-digital converter (ADC) using a distributed averaging correlated level shifting (DACLS) ring amplifier as its residue amplifier (RA). Compared to the prior CLS and ACLS techniques that reduce the RA gain error due to their finite open-loop gain, the proposed DACLS ring amplifier no longer requires an extra level-shifting capacitor ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C_{\mathrm {LS}}$ </tex-math></inline-formula> ) at the RA output, such that the RA bandwidth can be improved. Furthermore, instead of a single-level shift in the prior arts, the DACLS ring amplifier provides an option for multiple level shifts and thereby accomplishes a greater RA gain error reduction. In addition, a customized bypass-window scheme is applied, which can skip some power-wasting digital-to-analog converter (DAC) switchings by window detection and thus reduces the power consumption of the ADC. To reduce the bit-cycling time of the SAR conversion, a delay-reduced (DR) SAR logic is introduced to increase the ADC speed. The ADC chip is fabricated in 28-nm CMOS technology and occupies an active area of 0.013 mm2. At 130-MS/s and the Nyquist-rate input frequency, the measured SNDR is 72.5 dB, while the power consumption is only 0.82 mW. Without any calibration, the proposed ADC achieves a Walden and a Schreier figure-of-merit (FoM) of 1.8 fJ/conversion step and 181.5 dB, respectively. Compared to the prior-art ADCs with an input bandwidth ≥ 40 MHz and a SNDR > 68 dB, this work shows the best FoMs.

An Automatic Circuit Design Framework for Level Shifter Circuits

Although design automation is a key enabler of modern large-scale digital systems, automating the transistor-level circuit design process still remains a challenge. Some recent works suggest that deep learning algorithms could be adopted to find optimal transistor dimensions in relatively small circuitry such as analog amplifiers. However, those approaches are not capable of exploring different circuit structures to meet the given design constraints. In this work, we propose an automatic circuit design framework that can generate practical circuit structures from scratch as well as optimize the size of each transistor, considering performance and reliability. We employ the framework to design level shifter circuits, and the experimental results show that the framework produces novel level shifter circuit topologies and the automatically optimized designs achieve <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.8\times $ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.3\times $ </tex-math></inline-formula> lower power-delay product (PDP) than prior arts designed by human experts.