Voltage Follower Research Articles

Implementation of a Double-Path Flipped Voltage Follower Cell for Voltage Conveyors

Implementation of a Double-Path Flipped Voltage Follower Cell for Voltage Conveyors

Power quality improvement in BLDC motor drive using PFC converter

The use of brushless DC motors (BLDC) in low-power appliances is increasing because of their features of high efficiency, wide speed range, and low maintenance. This project deals with a power factor correction (PFC) based BL Landsman converter-fed brushless DC motor drive as a cost-effective solution for low-power applications. The speed of the BLDC motor is controlled by varying the DC-link voltage of the voltage supply electrical converter feeding the BLDC motor drive. A low-frequency switch of the VSI is used for achieving the electronic commutation of the BLDC motor for reduced switch losses. The PFC-based letter of the alphabet device is designed to control in discontinuous inductance current mode; therefore utilizing a voltage follower approach which needs one voltage sensing element for dc-link voltage management and PFC operation. The projected drive is meant to control a large variety of speed management with improved power quality at AC mains. The performance of the projected drive is valid with experimental results obtained on a developed epitome of a PFC device. This manuscript deals with the configuration of a power factor correction converter feeding a drive of brushless DC motors for medium and low-power equipment. The DC link voltage of the drive system is maintained by a single DC voltage actuator. Two control converters for the BLDC motor drive have been implemented. The control strategy is based on a PFC-Landsman converter-fed BLDC motor drive. Comparison has been made in PI controller-based converter in terms of minimizing ripple and improving the power factor of BLDC Motor drive. The proposed work has been implemented under MATLAB/Simulink environment

Improved circuitry and post-processing for interleaved fast-scan cyclic voltammetry and electrophysiology measurements

The combination of electrophysiology and electrochemistry acquisition methods using a single carbon fiber microelectrode (CFM) in the brain has enabled more extensive analysis of neurochemical release, neural activity, and animal behavior. Predominantly, analog CMOS (Complementary Metal Oxide Semiconductor) switches are used for these interleaved applications to alternate the CFM output between electrophysiology and electrochemistry acquisition circuitry. However, one underlying issue with analog CMOS switches is the introduction of transient voltage artifacts in recorded electrophysiology signals resulting from CMOS charge injection. These injected artifacts attenuate electrophysiology data and delay reliable signal observation after every switch actuation from electrochemistry acquisition. Previously published attempts at interleaved electrophysiology and electrochemistry were able to recover reliable electrophysiology data within approximately 10–50 ms after switch actuation by employing various high-pass filtering methods to mitigate the observed voltage artifacts. However, high-pass filtering of this nature also attenuates valuable portions of the local-field potential (LFP) frequency range, thus limiting the extent of network-level insights that can be derived from in vivo measurements. This paper proposes a solution to overcome the limitation of charge injection artifacts that affect electrophysiological data while preserving important lower-frequency LFP bands. A voltage follower operational amplifier was integrated before the CMOS switch to increase current flow to the switch and dissipate any injected charge. This hardware addition resulted in a 16.98% decrease in electrophysiology acquisition delay compared to circuitry without a voltage follower. Additionally, single-term exponential modeling was implemented in post-processing to characterize and subtract remaining transient voltage artifacts in recorded electrophysiology data. As a result, electrophysiology data was reliably recovered 3.26 ± 0.22 ms after the beginning of the acquisition period (a 60% decrease from previous studies), while also minimizing LFP attenuation. Through these advancements, coupled electrophysiology and electrochemistry measurements can be conducted at higher scan rates while retaining data integrity for a more comprehensive analysis of neural activity and neurochemical release.

A 4.65 [formula omitted]V/V line regulation, transient enhanced, capacitor-less LDO with ultra-low load current dependence

A capacitor-less low-dropout regulator (CL-LDO) based on an improved flipped voltage follower (FVF) cell with robust regulation capability and high transient response is presented. The line regulation (LNR) and load regulation (LAR) are enhanced by a stable DC operating point design and multiple feedback loops. A nested feed-forward gm-stage and a nulling resistor in the nested Miller compensation (NGRNMC) topology ensures stability in various challenging conditions. The proposed CL-LDO was designed in 0.18μm BiCMOS technology and occupied an area of 0.0582 mm2, with a typical input voltage range of 3.0 V–3.6 V and a load range of 0–100 mA. Post-simulation verification under various process, voltage, and temperature (PVT) conditions confirms the design’s robustness and reliability. The proposed design achieves the best figure of merit (FoM) of 1.69 mV among state-of-the-art designs, accompanied by a LNR of 4.65 μV/V and a LAR of 27.881 nV/mA.

A low power‐area low pass Gm‐C filter in biomedical analog front end for biosignal acquisition

SummaryIn this paper, a low‐power transconductor‐capacitor (Gm‐C) filter with programmable cutoff frequency is designed for electroencephalogram (EEG), electrocardiogram (ECG), and surface electromyography (sEMG) biosignals. The second‐order Butterworth low pass filter (LPF) is designed as an interface between an instrumentation amplifier (IA) and an analog‐to‐digital converter (ADC). The proposed Gm‐C filter suppresses out‐of‐band components and also plays an anti‐aliasing role. With the variable transconductance based on flipped voltage follower (FVF), the cutoff frequencies of 100 Hz, 560 Hz, and 1.5 kHz are obtained for EEG, ECG, and sEMG, respectively. This structure is highly accurate by using a robust and low‐power common mode feedback (CMFB). With 0.8 V supply voltage, the total power consumption of the filter is only 56 nW, 100 nW, and 221 nW for cutoff frequencies of 100 Hz, 560 Hz, and 1.5 kHz, respectively. The proposed Gm‐C filter is simulated in TSMC 65 nm CMOS technology and occupies an area of 0.12 mm2. The figure of merit (FOM) of the proposed filter is equal to 1.9 pW/pole.

A New Low-Voltage Second Generation Voltage Conveyor Using Merged Voltage Follower and DTMOS Techniques

A very simple, compact and low-power second generation voltage conveyor circuit using only eight transistors is proposed in this work. Voltage follower stage is implemented using merged voltage follower (MVF), offering very low output impedance. A simple current mirror forms the input stage of the proposed voltage conveyor. To further enhance the linearity, another circuit is proposed where input transistor in MVF is replaced with DTMOS (Dynamic Threshold Voltage MOSFET), giving [Formula: see text][Formula: see text]mV linearity range as compared to [Formula: see text][Formula: see text]mV of the first proposal. Proposed-II VCII provides reduced offset voltage due to decreased effective threshold of DTMOS, and gain bandwidth product of the circuit also improves. Simulation results are computed using 180-nmCMOS technology with supply voltage of [Formula: see text][Formula: see text]V to validate the proposed circuits. Proposed-I and proposed-II VCII consume 85.1[Formula: see text][Formula: see text]W and 97.5[Formula: see text][Formula: see text]W, respectively. An application of the proposed conveyors as “current to voltage converter”, is also presented.

Low-Voltage Current-Mode Full-Wave Rectifier Employing FVF-Biased MOS Translinear Loop

In this communication, a low-voltage complementary metal-oxide semiconductor (CMOS) current-mode full-wave rectifier (FWR), implemented from a flipped voltage follower-biased MOS translinear loop (FVF-MTL) is presented. The use of flipped voltage follower (FVF) minimizes the overall supply voltage demand by reducing the voltage headroom while maintaining the operation of the MOSFETs in strong inversion mode. The functioning of the proposed FWR circuit has been demonstrated through simulations carried out on Cadence Virtuoso software at [Formula: see text] CMOS technology at a supply voltage of 0.85[Formula: see text]V. The proposed FWR works over an input range of [Formula: see text] with a maximum linearity error of 3% in its transfer characteristics. The -3 dB bandwidth of the circuit has been found to be 54.95[Formula: see text]MHz. The minimum power and maximum power consumed by the circuit are 22.6[Formula: see text]nW and [Formula: see text], respectively. Post-layout simulations, Monte Carlo (MC), corner and temperature analyses have been carried out to estimate the performance and robustness of the proposed circuit.

Enhanced Power Factor Correction and Torque Ripple Mitigation for DC–DC Converter Based BLDC Drive

A novel approach to the design of power factor correction (PFC) and torque ripple minimization in a brushless direct current (BLDC) motor drive with a new pulse width modulation (PWM) technique is demonstrated. The drive was designed to have a better power factor (PF) and less torque ripple. On the other hand, the modified Zeta converter is used to enhance the power factor of the proposed system. The modified Zeta converter is operated in discontinuous inductor current mode (DICM) by using a voltage follower technique, which only needs a voltage sensor for power factor correction (PFC) operation and DC-link voltage control. The output voltage of the VSI is determined by switching patterns generated by the PWM-ON-PWM switching strategy, and it reduces the torque ripples. The proposed drive is developed and simulated in a MATLAB/Simulink environment. The power factor of 0.9999 is produced by the PFC modified zeta converter topology and the PWM-ON-PWM scheme reduce the torque ripple in the commutation region by 34.2% as compared with the PWM-ON scheme. This demonstrates the effectiveness of the suggested control method.

A CAFVF-based output-capacitor-less LDO with PSRR improvement by feed forward and negative capacitance

This paper presents an output-capacitor-less LDO regulator that is implemented in a 0.18μm CMOS process. It is based on an improved cascode flipped voltage follower that uses two buffer stages to improve loop stability and load current. The feed forward PSRR improvement technique and the equivalent negative capacitance PSRR improvement technique are proposed to improve the power supply rejection ratio (PSRR) performance up to 24 dB at 10 kHz and 38 dB at 100 kHz, respectively. The quiescent current is 27.7 μA, enabling a maximum load current of 50 mA with a dropout voltage of 200 mV. It also achieves excellent line regulation of 0.675 mV/V and load regulation of 8.2 μV/mA.

In-Memory Computing Integrated Structure Circuit Based on Nonvolatile Flash Memory Unit

Artificial intelligence has made people’s demands for computer computing efficiency increasingly high. The traditional hardware circuit simulation method for neural morphology computation has problems of unstable performance and excessive power consumption. This research will use non-volatile flash memory cells that are easy to read and write to build a convolutional neural network structure to improve the performance of neural morphological computing. In the experiment, floating-gate transistors were used to simulate neural network synapses to design core cross-array circuits. A voltage subtractor, voltage follower and ReLU activation function are designed based on a differential amplifier. An Iris dataset was introduced in this experiment to conduct simulation experiments on the research circuit. The IMC circuit designed for this experiment has high performance, with an accuracy rate of 96.2% and a recall rate of 60.2%. The overall current power consumption of the hardware circuit is small, and the current power consumption of the subtractor circuit and ReLU circuit does not exceed 100 µA, while the power consumption of the negative feedback circuit is about 440 mA. The accuracy of analog circuits under the IMC architecture is above 93%, the energy consumption is only about 360 nJ, and the recognition rate is about 12 μs. Compared with the classic von Neumann architecture, it reduces the circuit recognition rate and power consumption while meeting accuracy requirements.

Design of transient enhanced output-capacitor-less flipped voltage follower based LDO regulator with a fast control loop for wide range of capacitive loads

A fast low dropout (LDO) regulator based on flipped voltage follower (FVF) with impedance compensation, is presented. This LDO offers stable regulation over wide range of load capacitances starting from 10 pF to 10 nF. It provides an extended load regulation from 100 μA to 30 mA. This enhancement is achieved by incorporating a voltage combiner stage along with an active feed-forward into the regulating loop. Unconditional stability for wide range of loads is ensured with the help of Miller’s compensation with a nulling resistor by the use of on-chip 75 pF capacitor, 4.5 kΩ MOSFET resistor and a feed forward capacitor. The proposed LDO is verified with simulation in 45 nm CMOS process. For an input voltage of a 1.2 V–2 V, LDO offers a regulated output of 1.07 V, with a minimal drop out voltage. Under a load transient of 100 μA to 30 mA within 1ns of edge time, the undershoot and overshoot are limited respectively to 35 mV and 82 mV, with almost 295 ps of response time. The quiescent current excluding the control voltage generator is 81–112 uA, which provides excellent current efficiency. The simulated PSRR is −42 dB over the band of 10 Hz–10 kHz, −20 dB at 1 MHz over 100 uA–50 mA of load currents also across varying load capacitors of 10 pF–10 nF. The line regulation is approximately 1.35mV/ V and load regulation is around 2 μV/mA.

Single CDBA-based grounded parallel lossy inductor simulator circuits

Two new configurations for the realization of lossy grounded inductor each employing one current differencing buffered amplifier (CDBA), three resistors, a voltage follower and one grounded capacitor are presented. The realized inductances from the proposed configurations have independent tunability through a single resistor. The proposed circuits make use of the intrinsic current differencing property of CDBAs by not leaving any of its input terminals open or connected to ground. Both the presented circuits use grounded capacitor (which is particularly attractive for integrated circuit implementation) connected at the Z-terminal of CDBA which may also absorb the parasitic capacitance. The proposed lossy inductors can be used in applications such as low frequency sinusoidal oscillator, low pass filter (LPF) and band pass filter (BPF). Such examples may be suitable from the viewpoint of biomedical instrumentation and geo-physical applications. Non-ideal analysis has been carried out to support the theoretical propositions for both the proposed circuits. PSPICE simulation results with CMOS CDBA have been presented to establish the workability of the proposed lossy inductor structures. Experimental results using commercially available AD844 ICs have also been included to demonstrate the viability of the proposed lossy inductors based on CDBAs.

Design and Implementation of MPPT Solar System Based On the ANN & ANFIS

The project works with maximum power point tracking (MPPT) using the Perturb and Observe (P&O) algorithm. The P&O algorithm is implemented using the controller make up of logic components such as voltage follower, voltage inverter, differentiators, comparators, and X-OR gates. The solar energy harvested from solar panel is fed into the MPPT system to acquire maximum power output at the load. Typical solar panel works with low efficiency such < 15% thus, maximizing from the solar panel energy is a necessity to achieve optimum performance of solar energy. A simple MPPT system is built to maximize the power of solar panel. Key Word: Energy; Tracking; Solar Cells; Power; Temparature.

Perancangan dan Pembuatan Data Acquisition Device Sebagai Sistem Akuisisi Data untuk Kendali Mobil Formula Student

Data Acquisition Device (DAQ) is an electronic component used in formula student vehicles. To optimize the performance of the formula student vehicle and its driver, it is necessary to analyze and monitor the data acquisition system. Parameters acquired on the car include the position of the brake pedal/throttole and wheel speed.DAQ system has 5 input channels namely 3 analog input pins and 2 digital input pins, and 3 output channels, which is the controller pin, fault pin, and brake light pin. The DAQ system in this research is designed and made using Teensy 3.6, a signal conditioning circuit consisting of an RC low pass filter, voltage follower, non-inverting amplifier, and logic level shifter. DAQ system uses CANBUS to read and process sensor data. DAQ system can acquire data from the KTC Linear Motion Position sensor PZ-12-A-50P with an accuracy value of 99,91%; Hall-effect Rotary Position sensor RTY120LVNAX with an accuracy value of 99,94% for both the first and second sensors; and Proximity sensor LJ12A3-4-Z/BX with an accuracy value of 99,58% for the first sensor and 99,46% for the second sensor. DAQ is able to run controller signal processing, detect faults, and activate brake light signal according to FSAE rules.

Design of low voltage high output resistance current mirror

A current mirror design having high output resistance operating at low supply voltage is proposed in this paper. The low voltage operation is achieved using the flipped voltage follower for current mirroring. The circuit operates at low supply with high swing with low impedance node at its output. As low impedance is one the basic requirement of a current mirror, the flipped voltage follower when used as an input shows reduced impedance. However, the observed output resistance of conventional flipped voltage follower current mirror turns to be around 700K ohm, a low value. So, for its improvement a feedback loop is used at the output of proposed current mirror. This improves the output resistance significantly without deteriorating the other performances like bandwidth to a value of 401M ohm. The proposed current mirror results in input impedance in hundreds of ohms around 330 ohm and bandwidth of 2.4GHz comparatively higher than its conventional design. The complete design is carried out using 180 nanometer-based MOS transistors and the circuit runs at 0.5 volt of dual polarity.

Class AB Voltage Follower and Low-Voltage Current Mirror with Very High Figures of Merit Based on the Flipped Voltage Follower

The application of the flipped voltage follower to implement two high-performance circuits is presented: (1) The first is a class AB cascode flipped voltage follower that shows an improved slew rate and an improved bandwidth by very large factors and that has a higher output range than the conventional flipped voltage follower. It has a small signal figure of merit FOMSS = 46 MHz pF/µW and a current efficiency figure of merit FOMCE = 118. This is achieved by just introducing an additional output current sourcing PMOS transistor (P-channel Metal Oxide Semiconductor Field Effect Transistor) that provides dynamic output current enhancement and increases the quiescent power dissipation by less than 10%. (2) The other is a high-performance low-voltage current mirror with a nominal gain accuracy better than 0.01%, 0.212 Ω input resistance, 112 GΩ output resistance, 1 V supply voltage requirements, 0.15 V input, and 0.2 V output compliance voltages. These characteristics are achieved by utilizing two auxiliary amplifiers and a level shifter that increase the power dissipation just moderately. Post-layout simulations verify the performance of the circuits in a commercial 180 nm CMOS (Complementary Metal Oxide Semiconductor) technology.

High-Efficiency Interleaved Totem-Pole PFC Converter With Voltage Follower Characteristics

High power density, efficiency, control simplification, and robustness are highly demanded for power factor correction (PFC) converters. This paper proposes a totem-pole rectifier based on the switching cell with switching frequency modulation (SC-SFM). The SC-SFM features interleaved operation, soft commutation, and resistive characteristics with continuous conduction in the input inductor. The converter operates without needing sensors and a control loop for the current. Unlike conventional solutions or some sensorless converters, the converter does not require a fast control loop to shape the current since the current naturally follows the input voltage. Only one output voltage sensor and one input half-line cycle detector are required to achieve unitary power factor and regulated DC output voltage. A detailed analysis of the converter operation, including the operating principle, mathematical analysis, a small signal model, and control method, is presented, including the differences in operation from the conventional PFC rectifier with the diode bridge. Experimental results evaluate a 1-kW prototype with different switch technologies (IGBT, SiC, and GaN).

Analysis of Self-Bias Current Reference with BJT and its Application in Flipped Voltage Follower

Analysis of Self-Bias Current Reference with BJT and its Application in Flipped Voltage Follower

Potentiostat design keys for analytical applications

In this article the principles of potentiostat designs are discussed. Novel technical solutions for the design of electrochemical devices with a focus on portable applications are considered. Known solutions for analytical potentiostats are discussed, and the functionality of existing devices is analysed. Key points of the discussion include a brief introduction to specific terminology for potentiostat characterization, analysis of schematics, operation principles and requirements for basic units including control amplifier, voltage follower and transimpedance amplifier. Moreover, the substantial functions of potentiostat unit operation and corresponding limitations were described. The reasons for the inevitably high cost of versatile devices, as well as design recommendations for potentiostats, are also discussed. The proposed explanation will be helpful for potentiostats’ comprehensive design and application in analytical practice, for recognition and exclusion of artefacts from experimental data.

A feed-forward compensated FVF LDO regulator with no on-chip compensation capacitors

This paper proposes a capacitor-free Flipped Voltage Follower (FVF) Low Dropout (LDO) regulator. To stabilize the feed-back loop, the proposed multi-stage FVF LDO regulator does not require a Miller compensation capacitor or physical resistor. A capacitor-free internal structure improves closed-loop bandwidth while saving area in the LDO regulator. In this work, a large feed-forward transconductor (gmf) is proposed, which generates a strong left-half-plane (LHP) zero while consuming a small bias current. The large feed-forward transconductor boosts the LDO regulator’s DC gain and bandwidth. The proposed FVF LDO regulator is implemented in standard 130nm CMOS technology and achieves a unity gain frequency of more than 35 MHz while consuming a total quiescent current of 97μA. The proposed FVF LDO regulator has an active area of 0.0054mm2, which is less than many other LDO regulators that have been reported.