Voltage-controlled Resistance Research Articles

Adaptive impedance matching in microwave and terahertz metamaterial absorbers using PIN diodes and GaN HEMTs

Metamaterial absorbers allow electromagnetic waves to be converted into heat energy based on impedance matching. However, passive metamaterial absorbers exhibit fixed absorption characteristics, limiting their flexibility. This work demonstrates tunable microwave and terahertz absorbers by integrating adjustable resistors into the metamaterial units. First, a microwave absorber from 1 to 5 GHz was designed by embedding PIN diodes with voltage-controlled resistance. Calculations, simulations, and measurements verified two separate absorption peaks over 90% when optimized to a resistance of 250 Ω. The absorption frequencies shifted based on the resistor tuning. Building on this, a terahertz absorber was modeled by substituting gallium nitride high electron mobility transistors (GaN HEMTs) as the adjustable resistor component. The GaN HEMTs were controlled by an integrated gate electrode to modify the two-dimensional electron gas density, allowing resistance changes without external voltage terminals. Simulations revealed two absorption peaks exceeding 90% absorption at 0.34 THz and 1.06 THz by adjusting the equivalent resistance from 180 Ω to 380 Ω, and the tunable resistance is verified by DC measurement of single GaN HEMT in the unit. This work demonstrates how integrating adjustable resistors enables dynamic control over the absorption frequencies and bandwidths of metamaterial absorbers. The proposed geometries provide blueprints for tunable microwave and terahertz absorbers.

Grounded synthetic series lossy inductor simulator circuits employing single current differencing buffered amplifier

SummaryIn this communication, two new positive lossy series inductor simulator circuits using single current differencing buffered amplifier (CDBA), one capacitor, and three resistors are presented. In both the proposed circuits, the inductance value is independently controllable through a grounded resistor, which may be implemented using a voltage‐controlled resistor (VCR), facilitating electronic tuning. Moreover, one of the circuits presented utilizes the intrinsic resistance (internal resistance available at input ports p and n) of the CDBA, thereby enabling electronic control and establishing the inductor simulator as canonical. Both the circuits are analyzed for non‐ideal behavior by taking into account the parasitic elements of CDBA and compared with their ideal counterparts. To demonstrate the efficacy of the proposed series RL simulator circuits, SPICE simulations are performed using CMOS CDBA, and the performance of the proposed circuits is evaluated by designing a lead compensator. The simulation and experimental results of the proposed circuits, along with the application examples employing CDBA realized with the off‐the‐shelf available IC AD844, have also been corroborated.

Optimizing multi-level ReRAM memory for low latency and low energy consumption

Abstract With decreasing die size and the ability to store multiple bits in a single cell, resistive random access memory (ReRAM) can be used to increase storage density, making it a promising technology for the next generation of memory. However, multi-level write operations suffer from impairments such as large latency, high energy consumption, and reliability issues. In this paper, we study different mechanisms affecting the “multi-level incremental step pulse with verify algorithm” (M-ISPVA) on a 1-transistor-1-resistor (1T1R) model in transient simulation at the component and the circuit level with focus on resistance control and energy consumption during the entire process of state transitions. By dividing the M-ISPVA into a triggering and a controlling period, we discovered the transistor to operate in the ohmic region during the triggering period as a voltage-controlled resistance and in the saturation region during the controlling period as a voltage-controlled current limiter. Controlling the gate voltage in the triggering period can move the triggering point to a desired write voltage and in the controlling period can increase or decrease resistance steps per pulse to attain a desired speed of resistance change. In addition, the major energy portion is consumed for reset operation during triggering and for set operation during the controlling period. To optimize write performance, extra precaution must be taken when defining resistance states with target read-out current and gate voltage with the focus on evenly balanced latencies between all transitions. A direct multi-level write operation shows 67.5 % latency and 62.5 % energy saving compared to indirect ones, but suffers from only unidirectional control, making it non-feasible. In case of a 4 k bit memory, the more reliable M-ISPVA faces almost 37 % higher latency and energy compared to the basic ISPVA.

CMOS linear voltage‐controlled positive/negative floating resistance configuration and its application in realising a voltage controllable all‐pass filter

SummaryThis letter presents a general CMOS linear voltage‐controlled resistance (VCR) configuration, which can be configured as a voltage‐controlled floating positive resistance (VCFPR) and a voltage‐controlled floating negative resistance (VCFNR) by a simple artifice of changing two connections. The validity of this configuration has been demonstrated by SPICE simulations using 0.18‐μm CMOS process parameters. As an illustration of the utility of the proposed configuration, an application in which both VCFPR and VCFNR are utilised to realise a voltage tuneable all pass filter has been presented whose workability too has been demonstrated by SPICE simulations.

Phase synchronization between neurons under nonlinear coupling via hybrid synapse

Biological neurons and nonlinear circuits contain certain inner field energy, and an equivalent Hamilton energy function can be obtained to discern the dependence of firing modes on the energy flow. In this paper, a voltage-controlled resistor is used to connect two neural circuits, and hybrid synapse is activated to control the synchronization stability and mode transition in neurons under phase lock. Realistic stimuli can be combined signals within certain frequency band rather than simple periodic stimulus, and the firing patterns will show multiple modes by applying mixed signals. Similar coherence resonance is detected in an isolated neuron driven by the filtered signals. Therefore, chaotic signals are encoded to represent filtered waves with finite frequency band, and then the mixed signals are used to excite two neural circuits via nonlinear coupling. Hamilton energy for the coupled neurons via hybrid synapse is estimated to detect the controllability of synchronization between neurons. The nonlinear resistor along the coupling channel can reproduce the biophysical property of hybrid synapse accompanying with field coupling, which mainly contributes the energy exchange between neurons. It is confirmed that this hybrid synapse is effective to control the synchronization stability and phase lock even the neurons presenting with different firing patterns/modes. The results confirmed that nonlinear coupling via specific components is helpful to design hybrid synapse, and it is effective to block the bursting synchronization between neurons driven by filtered chaotic signals. Therefore, activation of this hybrid synapse can prevent the occurrence of seizure in nervous system.

New negative‐grounded capacitance multiplier circuits

SummaryIn this communication, three new negative‐grounded capacitance multiplier (NGCM) circuits employing a single current feedback operational amplifier (CFOA), two resistors, and a grounded capacitor (which is most suitable for parasitic absorption and also IC implementation point of view) are investigated. No matching constraints are required for any of the proposed circuit realizations. Out of the three proposed circuits, multiplication factor of one of the capacitance multiplier can be controlled electronically as the controlling resistor is grounded, which can easily be replaced by a voltage‐controlled resistor (VCR). Error analysis of the proposed NGCMs has been carried out, and the results have been compared with those obtained from ideal analysis. To substantiate the feasibility of the proposed circuits, macro model of CFOA has been used, and the simulations have been performed in Personal Simulation Program with Integrated Circuit Emphasis (PSPICE). Simulation results for frequency analysis, Monte‐Carlo analysis, and temperature analysis have been included for the theoretical justification. Noise analysis and power supply rejection ratio analysis have also been carried out for the proposed circuits. The multiplication factors of the proposed NGCMs have been obtained up to a maximum value of 2001. The impedance and phase of the proposed NGCM structures are insensitive with temperature. The functionality of the proposed structures has also been validated experimentally using commercially available IC AD844‐type CFOA.

A Subcircuit-Based Model for the Accumulation-Mode MOS Capacitor

The accumulation-mode metal-oxide-semiconductor (MOS) capacitor is commonly employed to implement MOS varactors in frequency-tuning circuits for radio frequency (RF) and analog applications. A subcircuit model for the accumulation-mode MOS (AMOS) capacitor based on the Berkeley Short-channel IGFET Model (BSIM) for the MOS field effect transistor (MOSFET) is presented. The proposed model accurately fits the capacitance-voltage (C-V) characteristics of an AMOS capacitor fabricated in a submicron CMOS process over the full range of operating gate voltages. The model also accounts for the impact of the distributed series resistance on the transient response of the AMOS capacitor. Notably, the gate capacitance and the associated series resistance are modeled as a distributed resistor-capacitor (RC) network to derive a subcircuit-based model with the bias-dependent resistance of the accumulation layer modeled as a voltage-controlled resistor (VCR). The proposed model is evaluated based on SPICE simulation of the intrinsic transient response of the AMOS capacitor using a basic circuit, representing the distributed RC network associated with the MOS device structure. Fine tuning of the effective series resistance in the subcircuit model can be achieved by fitting the measured data characterizing the charge–discharge behavior of the AMOS capacitor to the simulated data characterizing the intrinsic transient response generated by SPICE.

Laser-Scribed Graphene (LSG) Fabrication Method for Microwave Circuit Applications

In this letter, a laser-scribed graphene (LSG) fabrication method is used to create graphene to be used in a microwave application, for example, a voltage-tunable microstrip attenuator. Graphene used in microwave circuits, such as tunable attenuators, usually focuses on using exfoliated graphene, deposited graphene nanoplatelets, or microwave irradiation. It will be demonstrated that the fabrication of LSG from graphene oxide on standard double-sided FR-4 copper-clad substrate can be used as a voltage-controlled resistor that results in a tunable microstrip attenuator across the microwave frequencies from 50 MHz to 5.5 GHz.

Wheatstone bridge based offset cancelling method utilizing a JFET as a voltage-controlled resistor

We designed and investigated an offset cancelling circuit based on a Wheatstone bridge at the output of a Hall-effect sensor. This circuit not only cancelled the offset voltage caused by unintentional Hall probe misalignment but also provided a voltage gain. The Wheatstone bridge circuit consisted of a JFET, two fixed resistors and a variable resistor. In the absence of magnetic field, the JFET was used as a voltage-controlled resistor and its channel resistance was determined by the Hall offset voltage. To compensate the node voltage induced in the JFET channel with the non-zero Hall offset voltage, the variable resistor in the bridge circuit was adjusted to produce the cancelled output voltage between the two bridge nodes. The difference output of the bridge nodes acted as the offset cancelled Hall voltage. When the magnetic field was applied, the branch with the JFET acted as a common source amplifier with the input from the measured Hall voltage. Therefore, the difference output represented the amplified offset cancelled Hall voltage with the magnetic field. The operating point of the amplifier was chosen for linearity and its gain was measured to be 26.4.

Characterization and Modeling of the Polysilicon Emitter Contact for Circuit Simulation

The emitter contact in bipolar transistors with polysilicon emitters has been characterized based on an improved open-collector (OC) method, which allows extraction of the nonlinear I-V characteristics of the resistance presented by the poly-/monocrystalline emitter interface. The nonlinear characteristics of the interfacial polysilicon-emitter resistance at low currents are modeled using an approximate rectangular-barrier tunnel junction model to extract an upperbound estimate for the thickness of the oxide layer at the poly-/monocrystalline contact. Having verified that the extracted data based on the improved OC method are consistent with the first-principles rectangular tunnel junction model, a data-driven model accounting for the bias-dependence of the emitter series resistance is presented, which employs a voltage-controlled resistor (VCR) to enable the efficient simulation of the effect of the interfacial nonlinearity as well as the substrate bias. SPICE simulations indicate that the VCR-based model for the emitter resistance accurately predicts the measured I-V characteristics obtained using the improved OC method. The utility of a subcircuit-based model explaining the experimentally observable effect of the substrate bias on the behavior of the emitter resistance is also evaluated for circuit simulation.

CNTFET based Voltage Mode MISO Active only Biquadratic Filter for Multi-GHz Frequency Applications

A new voltage mode, carbon nanotube field-effect transistor (CNTFET) based multiple input single output active only biquadratic filter (AOBF), is presented. The proposed AOBF employs simple and compact single ended transconductance elements, voltage-controlled resistor (VCR) and varactor. The proposed AOBF provides band-pass filter, band-reject filter, all-pass filter, high-pass filter and low-pass filter responses, just by selecting the appropriate inputs. The AOBF operates at low-voltage supply of 0.7 V and suitable for integration due to absence of any external passive component. The realized AOBF also enjoys the attractive features of orthogonal voltage-controlled tuning of its pole-Q and pole-ωo, low incremental sensitivity performance and suitability for multi-GHz frequency applications. The pole-Q of the filter is controlled through CNTFET-based VCR while the pole-ωo is controlled through the CNTFET-based varactor. To validate the performance, HSPICE simulation on the designed AOBF was carried out using Stanford CNTFET model at 16 nm technology node. The simulation results thus obtained, justify the theory proposed.

A Closed-Loop Capacitance-to-Frequency Converter for Single-Element and Differential Capacitive Sensors

A novel closed-loop switched-capacitor (SC) capacitance-to-frequency converter (CFC) is presented in this article. The proposed CFC is capable of measuring from either a single-element or a differential capacitive sensor (DCS), providing ratio and ratiometric outputs, respectively. Most of the existing autobalancing schemes for capacitive sensors use the closed-loop approach but require precise sinusoidal ac excitation and provide an analog output that is sensitive to parasitic capacitances. Also, the use of voltage-controlled resistors (VCRs) in many of these schemes limits the linearity and accuracy of their output. The SC-CFC presented in this article employs a simple dc reference for excitation and gives a digital output that is insensitive to parasitic capacitances, by virtue of design. Additionally, the output is linear, irrespective of the sensor characteristic, and independent of the nominal value of the sensor. This feature, along with its compatibility with single-element and DCSs, facilitates its ease of integration with a wide range of capacitive sensors. The CFC has a one-time correction mechanism that significantly reduces the impact of component mismatch. The prototype of the proposed scheme exhibits a maximum nonlinearity error (NLE) of 0.24%, a resolution of 12.59 effective number of bits (ENOB), and a rise time of 6 ms. In addition, the proffered design is fit for integrated circuit (IC) fabrication as it employs an SC approach.

A 0.35μm Low-Noise Stable Charge Sensitive Amplifier for Silicon Detectors Applications

The Charge Sensitive Amplifier (CSA) is the key module of the front-end electronics of various types of Silicon detectors and most radiation detection systems. High gain, stability, and low input noise are the major concerns of a typical CSA circuit in order to achieve amplified susceptible input charge (current) for further processing. To design such a low-noise, stable, and low power dissipation solution, a CSA is required to be realized a complementary metal-oxide-semiconductor (CMOS) technology with a compact design. This research reports a low-noise highly stabile CSA design considerations for Silicon detectors applications, which has been designed and validated in TSMC 0.35um CMOS process. In a typical CSA design, the detector capacitance and the input transistor’s width are the most dominating parameters for achieving low noise performance. Therefore, the Equivalent Noise Charge (ENC) with respect to those parameters has been optimized, for a set of detector capacitance from 0.2pF – 2pF. However, the parallel noise of the feedback was removed by adopting a voltage-controlled NMOS resistor, which in turn helped to achieve high stability of the circuit. The simulation results provided a baseline gain of 9.92mV/fC and show that ENC was found to be 42.5e – with 3.72 e – /pF noise slope. The Corner frequency exhibited by the CSA is 1.023GHz and the output magnitude was controlled at -56.8dB; it dissipates 0.23mW from with a single voltage supply of 3.3V with an active die area of 0.0049 mm 2 .

A Dual-Differential Subtractor-Based Auto-Nulling Signal Conditioning Circuit for Wide-Range Resistive Sensors

Analog signal conditioning circuit based on dual differential subtractor for wide range resistive measurement of single element resistive sensor is presented in this paper. The differential output from the sensor and a voltage-controlled reference resistor is followed by an auto-nulling technique, which helps to achieve high accuracy and wide dynamic range by generating a control voltage proportional to the sensor resistance. The presented automatic approach not only enhances the auto-nulling range but also ensures constant sensitivity. The interface design provides high accuracy, fast and linear response at the same time avoids drawbacks of lead wire variations. A prototype PCB of the proposed circuit is fabricated and tested. The experimental result shows that the circuit can measure a wide range of resistance (20 $\text{k}\Omega $ - 1.1 $\text{M}\Omega$ ) with relative error less than 0.78%, compared to other bridge-based circuits which are capable of measuring the maximum resistance of up-to 10 $\text{k}\Omega $ for the same accuracy. Multiple variations of the proposed circuit are designed and experimentally tested for verifying the tunability of the circuit in terms of the sensitivity and the range of resistance measurement. The prototype circuit is also interfaced with an in-house fabricated MEMS-based ammonia sensor, proving its efficacy in resistive sensor system development.

An Active Resistor With a Lower Sensitivity to Process Variations, and its Application in Current Reference

A novel active resistor circuit offering less sensitivity to process and temperature variations without any extra trimming is proposed. The circuit consists of two accurately matched, high resistance polysilicon (hripoly) resistors and a voltage-controlled MOS resistor, and it is designed for the industrial temperature range (-20 °C to 85 °C) in the TSMC 180 nm general-purpose process. The actual performance of the circuit is analyzed by using the Corner and Monte Carlo analyses that comprise two thousand samples for the global and local process variations. The maximum error in the resistor value is ±6.2 %, with the standard deviation of σ = 1.2 %. The proposed active resistor reduces the maximum error from ±15 % to ±6.2 % when the both the process and the temperature variations are considered without trimming. As an application, a transconductor and a current reference based on the novel active resistor are introduced, and their accuracy-related performance is studied.

A large dynamic range floating memristor emulator with equal port current restriction

In this paper, a large dynamic range floating memristor emulator &#x0028 LDRFME &#x0029 with equal port current restriction is proposed to be achieved by a large dynamic range floating voltage-controlled linear resistor &#x0028 VCLR &#x0029 . Since real memristors have not been largely commercialized until now, the application of a LDRFME to memristive systems is reasonable. Motivated by this need, this paper proposes an achievement of a LDRFME based on a feasible transistor model. A first circuit extends the voltage range of the triode region of an ordinary junction field effect transistor &#x0028 JFET &#x0029 . The idea is to use this JFET transistor as a tunable linear resistor. A second memristive non-linear circuit is used to drive the resistance of the first JFET transistor. Then those two circuits are connected together and, under certain conditions, the obtained &#x201C resistor &#x201D presents a hysteretic behavior, which is considered as a memristive effect. The electrical characteristics of a LDRFME are validated by software simulation and real measurement, respectively.

A Class of Single-CFOA-based Sinusoidal Oscillators

A class of second order sinusoidal oscillators is presented which employs a single Current feedback-operational amplifier, four capacitors and four to five resistors which can be realized by CMOS linear voltage controlled resistors (VCR). The proposed circuits are simultaneously single resistance controlled oscillators (SRCO) as well as single capacitor controlled oscillators (SCCO) providing independent control of condition of oscillation and frequency of oscillation through independent resistors as well as independent capacitors. To the best knowledge of the authors, any single-CFOA-based oscillators which are simultaneously SRCOs as well as SCCOs have not been reported in the literature earlier. SPICE simulation results using 0.18μm CMOS technology have been given which confirm the validity of the proposed circuits.

Voltage-Controlled Synthetic Inductors for Resonant Piezoelectric Shunt Damping: A Comparative Analysis

In this paper, the design, simulations, and experimental results related to new analog circuits for voltage controlled synthetic inductors (VCSI) are presented. The new circuits based on a generalized impedance converter (GIC) are proposed for adaptive resonant piezoelectric shunt damping. The VCSIs are implemented using (1) an analog multiplier and (2) an operational transconductance amplifier (OTA) as voltage-controlled resistor. The simulation and experimental results for the new proposed VCSIs are presented and a comparative analysis follows. The proposed VCSIs work in a stable manner in parallel with negative impedance converters (NIC) to enhance structural damping in resonant piezoelectric resistive-inductive shunt applications. The behavior of the synthetic inductor is identical to a real inductor only in a specific frequency range and this situation can explain the reported spreading performance in the literature for resonant piezoelectric shunt damping. The simulation results are validated by a group of experimental investigations that confirm the improved stability and linearity of the new circuits proposed as VCSIs. Experimental results show that the VCSI based on an analog multiplier have an enhanced linearity in comparison with the OTA version in a limited voltage control range.

Dual-Message Amplitude Modulation (DMAM)

In this paper, a new method is proposed for AM modulation of two separate messages (dual message). The proposed method uses only one carrier and does not need any transformer or multiplexer device, while the existing methods need two carriers or a transformer or a multiplexer device for modulating a dual message. The procedure of this modulation is quite simple. First, the carrier signal is divided into positive and negative half cycles. Then, one of the message signals is inserted into positive half cycles by a simple voltage-controlled resistor (e.g., a JFET in the linear region). Another message signal is inserted into negative half cycles using the same process. Finally, the half cycles are added together and the resultant signal would have two different envelopes on negative and positive half cycles. Detection of these two messages is easy too. The demodulator consists of two simple diode detectors. One of them gets the message signal from positive half cycles, and the other gets the negative half cycles signal. Altogether, the most important advantages of this design compared to the existing methods for modulating a dual message are less power consumption and more simplicity of modulating and demodulating procedures and circuits. In addition, this method decreases the cost of the modulator system.

Fully-differential current-mode higher order filters using all grounded passive elements

In this paper the realization of nth order (n ≥ 3) fully-differential current-mode filters using Current Differencing Current Conveyors (CDCC) has been presented which results in circuits employing all grounded passive elements. In contrast to earlier known realizations of fully-differential filters which invariably require more than one capacitors per pole, the proposed realization employs only one capacitor per pole. The cut-off frequency of the realized filter can be electronically tuned when all the grounded resistors associated with the integrators are implemented by identical CMOS grounded voltage-controlled-resistors (VCR) driven by a common control voltage. The methodology has been illustrated by realizing a fifth order Butterworth filter as a specific example whose workability has been verified using SPICE simulations in 0.18 µm TSMC technology. A reduced-component-version of the designed fifth order Butterworth filter has also been presented which also employs all grounded RC components but does not have electronic-tunability. Some representative simulation results have been included.