Modular adders are very crucial components in the performance of residue number system-based applications. Most of the work published so far has been restricted to modulo (2 n ± 1) adders or modulo-specific adders. Less work has been dedicated to modulo-generic adders. This work presents new designs for modulo (2 n ± K) adders, where K is any integer in the range of 3 ≤ K <; 2 n-1 . The proposed structure merges two binary adder structures and maximises sharing of components, wherever possible. This merger permits shorter cell-interconnections, which results in space wastage reduction. Additionally, tristate-based multiplexers (MUXs) are used in lieu of the more demanding gate-based MUXs. As examined over a very practical range of n, 7 ≤ n ≤ 15, and based on a 65 nm VLSI realisation, the circuit layouts of the proposed adders outperform considerably the most recent and competitive functionally identical published works. On average, the proposed designs have shown reductions in area, time, power, and energy of 23.7, 13.8, 22.9, and 33.6%, respectively.