Low-Jitter CMOS Digital PLL for the generation of the clock in synchronous serial communication systems

Abstract

The major building block of linear systems is the Phased Locked-Loop(PLL). Contrasting to analog PLL, the clock period profile of digital PLL (DPLL) is often segmented. Hence the phase and/or frequency tracking of traditional PLL’s may suffer from large jitter when Voltage Controlled Oscillator (VCO) operating point shifts from one clock period segment to another. To address this issue, a Low-Jitter CMOS Digital PLL for the generation of the clock in synchronous serial communication systems is presented in this paper. The design of the PLL will be implemented by considering important CMOS parameters like propagation delay, jitter performance, and power dissipation. Designing of digital PLL includes the design of a phase detector, LPF, Error amplifier, and VCO. The VLSI realization of digital PLL is implemented using the TANNER EDA software tool using a 0.18μm CMOS process.