A design method for digital phase-locked loop

Abstract

The design method of the digital phase-locked loop is presented,according to the parameters of the center frequency, the loop filter bandwidth, etc. The modules,phase detector(PD), loop filter(LF), voltage controlled oscillator(VCO),have the similar behavior with that of the analog phase-locked loop(APLL) by using Laplace transform and bilinear transformation. For the case of lacking QuartusII license for numerical controlled oscillator(NCO) IP core, It can be replaced by the module designed by using triangle transform which is high-precision. Since enormous numbers of LEs in FPGA will be occupied by the multiplier of filters, the optimization algorithmis presented utilizingaddition operation and shifting operation rather than multiply operation, which reduces resources used on the system. The design result is simulated and realized on FPGA development board, which confirms that the design method is feasible. Introduction Phase-locked loop is widely used in the fields of electronics, communication, measurement and control, and automatic control. With the development of modern digital circuit technology, in the aspect of communication and control method of complex information processing can be implemented with the widely application of the microprocessor and VLSI. Phase-locked loop, as an important module in the communication fields, has the advantages of digital circuit in high reliability, low price, small volume and etc. Phase-locked loop is compatible with the digital circuit with better portability. Therefore, people pay more attention to the phase of the PLL, so that it is developed rapidly. With the development of digital devices, digital phase-locked loop is applied to signal processing, modulation and demodulation, weak signal detection, frequency synthesis and so on. Compared with the traditional analog phase-locked loop, the digital phase-locked loop does not have the case of temperature drift. The design circuit is simply, meanwhile, filter parameters and the numerical control oscillator source are controlled by the code. It is easy to build a variety of high order loop PLL. In this paper, according to the design example, design the parameters of the analog phase-locked loop. The digital processing of the analog parts is with the bilinear transformation. And use FPGA to simulate and implement it. Basic theory of phase-locked loop A typical phase-locked loop system is consist of three basic circuit components: Phase detector, loop filter and voltage controlled oscillator. As shown in Figure 1. Phase-detector detect phase deviation between input signal and feedback signal. Multiply the input signal with sinusoidal signal generated by a voltage controlled oscillator. Then the low pass filter is used to filter out the 4th National Conference on Electrical, Electronics and Computer Engineering (NCEECE 2015) © 2016. The authors Published by Atlantis Press 1471 radio-frequency component and get the phase difference between the input signal and the signal generated by the local oscillator. The phase difference is used as the control signal, controlling the voltage controlled oscillator by the correction network control network and using a negative feedback mechanism to reduce or eliminate the phase deviation of the input signal and the local oscillator signal. Fig 1.typical phase-locked loop The digital phase-locked loop samples the analog input signal by the A/D into the FPGA. In FPGA, a phase detector, loop filter, and a numerical control oscillator module are built, making it to meet the same or similar operating performance of the analog filter. Requirements of design examples Designing an ideal two order loop digital phase-locked loop, carrier-frequency is 10 , maximum modulating angular frequency is 103π rad/s, 400 2π rad/s, 0.707。 According to the design requirements, the natural resonance frequency is: . 50π rad/s (1) Tap parameters of loop filter: 0.10053 (2)