Floorplan design is the first stage of VLSI layout design and perhaps the most important one. We consider the problem of determining a set of implementations that minimize the total area of spiral floorplans. The best known technique needs O (n3 log n) time, O (n3) space and generates O (n3) possible implementations of the floor rectangle. In this paper, we present an improved algorithm for solving the area optimization problem of spiral floorplans. Our algorithm computes the optimal implementations of the basic rectangles in O (n2 log n) time and O (n2) space, where each of the five basic rectangles has n implementations. The improvements on both time and space are crucial when multi-level spiral floorplans are considered.