Minimizing total wire length during 1-dimensional compaction

Abstract

Minimizing the total wire length is an important objective in VLSI layout design. In this paper we consider the problem of minimizing the total wire length during 1-dimensional (1-D) compaction. Assume we are given a layout containing n h horizontal wires, n v vertical wires, and rectilinear polygonal layout components composed of n r vertical edges. We present an O( n h· n log n) time algorithm for generating, from the constraint graph corresponding to the initial layout, a layout of minimum total wire length, n≤ n v + n r. Our algorithm generates, among all the layouts having minimum total wire length, one of minimum layout width, assuming that compaction is done along the horizontal direction. We also consider a number of other compaction problems in which a relationship between the layout width and the total wire length is specified. For example, we present an O( n h· n log n) time algorithm to determine a layout minimizing the objective function α · w + β · l, where w is the layout width and l is the total wire length, α, β > 0; i.e., we consider optimizing a tradeoff function between the layout width and the total wire length.