Abstract
In VLSI physical design automation minimization of total (vertical) wire length is one of the most important problems as it reduces the cost of physical wiring required along with the electrical hazards of having long wires in the interconnection, power consumption, and signal propagation delays. Since the problem of computing minimum wire length routing solutions in no-dogleg reserved two- and four-layer channel routing is NP-hard, it is interesting to develop heuristic algorithms that compute routing solutions of as minimum total (vertical) wire length as possible. In this paper we develop two algorithms to minimize the total (vertical) wire length in channel routing problem. First we develop an efficient re-router Further_Reduced_Wire_Length (FRWL) to optimize the wire length in the reserved two-layer (VH) no-dogleg channel routing model and then we develop a next algorithm Four_Layer_Reduced_Wire_Length (FLRWL) to optimize the total (vertical) wire length in the reserved four-layer (VHVH) no-dogleg Manhattan routing model. Experimental results computed for available benchmark instances are greatly encouraging.
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