An Efficient Algorithm for Reducing Wire Length in Three-Layer Channel Routing

Abstract

In VLSI physical design automation, channel routing problem (CRP) for minimizing total wire length to interconnect the nets of different circuit blocks is one of the most challenging requirements to enhance the performance of a chip to be designed. Interconnection with minimum wire length occupies minimum area and has minimum overall capacitance and resistance present in a circuit. Reducing the total wire length for interconnection minimizes the cost of physical wire segments required, signal propagation delays, electrical hazards, power consumption, the chip environment temperature, the heat of the neighboring interconnects or transistors, and the thermal conductivity of the surrounding materials. Thus, it meets the needs of green computing and has a direct impact on daily life and environment. Since the problem of computing minimum wire length routing solutions for three-layer no-dogleg general channel instance is NP-hard, it is interesting to develop heuristic algorithms that compute reduced total wire length routing solutions within practical time limit. In this paper, we have developed an efficient polynomial time graph-based heuristic algorithm that minimizes the total wire length for most of the benchmark channel instances available in the reserved three-layer no-dogleg Manhattan channel routing model. The results we compute are highly encouraging in terms of efficiency and performance of our algorithm in comparison to other existing algorithms for computing the same.