An efficient high performance parallel algorithm to yield reduced wire length VLSI circuits

Abstract

Green technology is a new research area in electronics, which meets the needs of society and explores the ability of VLSI circuits and embedded systems to positively impact the environment. In VLSI physical design automation, channel routing is a fundamental problem but reducing the total wire length for interconnecting the nets of different circuit blocks is one of the most challenging requirements to enhance the performance of a chip to be designed. Reducing the total wire length for interconnection not only minimizes the cost of the physical wire segments required, but also reduces the amount of occupied area for interconnection, signal propagation delays, electrical hazards, power consumption, heat generation, and over all the parasitics present in a circuit. Thus it has a direct impact on daily life and environment. Channel routing problem for wire length minimization is an NP-hard problem. Hence as a part of developing an alternative, we modify the existing graph theoretic framework Track_Assignment_Heuristic (TAH) to reduce the total (vertical) wire length. In this paper we propose an efficient polynomial time graph based parallel algorithm to reduce the total wire length without radically increasing of required area for interconnection in the reserved two-layer no-dogleg Manhattan channel routing model. The performance and efficiency of our algorithm is highly encouraging for different well-known benchmarks channels.