A graph theoretic approach to minimize total wire length in channel routing

Abstract

Minimization of total (vertical) wire length in VLSI physical design automation is one of the most important topics of current research. As fabrication technology advances, devices and interconnection wires are placed in closer proximity and circuits operate at higher frequencies. At the same time, delay is a factor that suspends a desired signal in conveying it to its destination in a proper time. This factor is directly proportional to the length of the interconnecting wire segments involved (Pal, R. K., Multi-Layer Channel Routing: Complexity and Algorithms, Narosa Pub. House, 2000). Pal et al. (see Proc. 8th VSI/IEEE Int. Conf. on VLSI Design, p.202-7, 1995) developed a purely graph theoretic framework, designated as TAH (track assignment heuristic), for computing routing solutions using the minimum possible area. We compute routing solutions with reduced total wire length using the TAH framework. The algorithm is used for computing two-layer no-dogleg routing solutions for most of the well-known benchmark channels. The performance of our algorithm is highly encouraging.