Abstract
AbstractThe simulated annealing method is concerned with the large‐scale combinational optimization problem such as VLSI layout design. It aims at arriving at the global optimum without being captured by the local minimum, by the probabilistic optimization based on the stochastic process. This paper considers the idle area between blocks and proposes a method of handling the block placement problem, where the simulated annealing is applied to the optimization. The result of the proposed method is compared with the result obtained by the constant‐ pressure Monte Carlo method, which is one of the block placement methods with simulated annealing. It is seen that the proposed method can arrive at an almost equivalent result, even though the number of parameters is less and the determination of the parameters requires less time.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: Electronics and Communications in Japan (Part III: Fundamental Electronic Science)
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
