CMOS VLSI Circuits Research Articles

Retraction Note: Adaptive wavelet ELM-fuzzy inference system-based soft computing model for power estimation in sustainable CMOS VLSI circuits

Retraction Note: Adaptive wavelet ELM-fuzzy inference system-based soft computing model for power estimation in sustainable CMOS VLSI circuits

Test Power Reduction through Reordering Algorithm Implementation and Advancements in BIST Architecture

Due to the reduction in transistor size, test engineers face a severe issue in power minimization. VLSI circuit's power dissipation has become a vital concern due to the switching activity of the Circuit Under Test (CUT). Switching activity is a significant factor in determining power consumption for CMOS VLSI circuits. In this paper, we formulate a distance estimation technique and reordering using the Tversky index. Here, the distance between the test vectors is calculated using the Tversky index with the formation of an adjacency matrix, and reordering is performed. The experimental results of the proposed method have been compared to different distance measures and existing techniques. It shows that the switching activity is reduced from 52.5% to 21.5%, and the average power reduction is from 42% to 14.6% when the distance is estimated on reordering using the Tversky index measure. Thus, the Tversky index distance measure performs better than the Hamming, gray, and Linear feedback shift register (LFSR) methods. Switching activity estimation for complex ISCAS circuits has been performed and compared with existing methods for superior performance. We have also developed a Built in Self-Test (BIST) for the C17 benchmark circuit, which uses the Tversky counter as a test pattern generator using the TANNER EDA tool. Thus, an efficient deterministic BIST for the C17 benchmark circuit was designed to detect all the stuck-at faults, and the same procedure can be used to create BIST for all CUT and precomputed test sets for real-time field testing.

Design of energy efficient domino logic circuit using lector technique

ABSTRACT Calculating power and delay in VLSI circuits are two main challenges in designing CMOS VLSI circuits. The manuscript proposes a lector technique-based foot-driven stack transistor domino logic for power and delay reduction. The lector technique uses two leakage-controlled transistors, PMOS and NMOS. The gate terminal of PMOS is connected to the source of NMOS, and the gate terminal of NMOS is connected to the source of PMOS. NMOS transistor N5 is used in the proposed circuit, driven by a dynamic node, which helps to reduce the power. This manuscript uses the proposed technique to design a buffer, two-input – AND gate, OR gate, and XOR gate circuits. The logic gates are simulated on the gpdk 45 nm cadence virtuoso software tool. The simulation result shows that the proposed domino logic circuit significantly reduces power, delay, energy, and leakage current. Monte Carlo analysis is performed to study the mean and standard deviation of the proposed circuit with 1000 samples.

Experimental Study of Algorithms for Minimization of Binary Decision Diagrams using Algebraic Representations of Cofactors

BDD (Binary Decision Diagram) is used for technology-independent optimization, performed as the first stage in the synthesis of logic circuits in the design of ASIC (application-specific integrated circuit). BDD is an acyclic graph defining a Boolean function or a system of Boolean functions. Each vertex of this graph is associated with the complete or reduced Shannon expansion formula. Binary decision diagrams with mutually inverse subfunctions (cofac-tors) are considered. We have developed algorithms for finding algebraic representations of cofactors of the same BDD level in the form of a disjunction or conjunction of other inverse or non-inverse cofactors of the same BDD level. The algorithms make it possible to reduce the number of literals by replacing the Shannon expansion formulas with simpler logical formulas and to reduce the number of literals in the description of a system of Boolean functions. We propose to use the developed algorithms for an additional logical optimization of the constructed BDD representations of systems of Boolean functions. Experimental results of the application of the corresponding programs in the synthesis of logic circuits in the design library of custom VLSI CMOS circuits are presented.

Low Power VLSI Design Techniques: A Review

Since CMOS technology consumes less power it is a key technology for VLSI circuit design. With technologies reaching the scale of 10 nm, static and dynamic power dissipation in CMOS VLSI circuits are major issues. Dynamic power dissipation is increased due to requirement of high speed and static power dissipation is at much higher side now a days even compared to dynamic power dissipation due to very high gate leakage current and subthreshold leakage. Low power consumption is equally important as speed in many applications since it leads to a reduction in the package cost and extended battery life. This paper surveys contemporary optimization techniques that aims low power dissipation in VLSI circuits.

Design of low-power CMOS VLSI circuits using multi-objective optimization in genetic algorithms

This paper presents a design CAD tool for automated design of digital CMOS VLSI circuits. In order to fit the circuit performance into desired specifications, a multi-objective optimization approach based on genetic algorithms (GA) is proposed and the transistor sizes are calculated based on the analytical equations describing the behavior of the circuit. The optimization algorithm is developed in MATLAB and the performance of the designed circuit is verified using HSPICE simulations based on 0.18µm CMOS technology parameters. Different digital integrated circuits were successfully designed and verified using the proposed design tool. It is also shown in this paper that, the design results obtained from the proposed algorithm in MATLAB, have a very good agreement with the obtained circuit simulation results in HSPICE.

Design of low-power CMOS VLSI circuits using multi-objective optimization in genetic algorithms

Design of low-power CMOS VLSI circuits using multi-objective optimization in genetic algorithms

Machine Learning Based Power Estimation for CMOS VLSI Circuits

ABSTRACT Nowadays, machine learning (ML) algorithms are receiving massive attention in most of the engineering application since it has capability in complex systems modeling using historical data. Estimation of power for CMOS VLSI circuit using various circuit attributes is proposed using passive machine learning-based technique. The proposed method uses supervised learning method, which provides a fast and accurate estimation of power without affecting the accuracy of the system. Power estimation using random forest algorithm is relatively new. Accurate estimation of power of CMOS VLSI circuits is estimated by using random forest model which is optimized and tuned by using multiobjective NSGA-II algorithm. It is inferred from the experimental results testing error varies from 1.4% to 6.8% and in terms of and Mean Square Error is 1.46e-06 in random forest method when compared to BPNN. Statistical estimation like coefficient of determination (R) and Root Mean Square Error (RMSE) are done and it is proven that random Forest is best choice for power estimation of CMOS VLSI circuits with high coefficient of determination of 0.99938, and low RMSE of 0.000116.

LOW POWER DIGITAL CMOS VLSI CIRCUITS DESIGN WITH DIFFERENT HEURISTIC ALGORITHMS

The growing demand for portable computing devices leads to new electronic systems fulfilling the requirements for the low power dissipation in the chip. Although, reduction of supply voltage is one of the most effective techniques of decreasing the power consumption in digital CMOS VLSI circuits it results in chip throughput degradation. This paper presents three versions of the Inserting Idle Operation with Interchanging heuristic algorithm, namely simple IIOI, MAximal RELativity (MAREL) and UNIform LOad (UNILO). They are applied to the high-level synthesis of CMOS VLSI circuits with power reduction. Comparison of the obtained results for the chosen set of benchmarks show the different levels of power reduction obtained by different algorithms applied. For different benchmarks the power reduction reaches up to 15%, and up to 68% with extending latency by 50%.

Process, Voltage, and Temperature Aware Analysis of ISCAS C17 Benchmark Circuit

High leakage currents such as sub-threshold leakage, junction leakage, and gate leakage currents have become prominent sources of power consumption in CMOS VLSI circuits due to rapid technology scaling in the nanometer regimen accompanied by supply voltage reduction. Consequently, in the nanometer regime, it is imperative to estimate and reduce leakage capacity. However, this continuous aggressive scaling makes the CMOS circuits more prone to Process, Voltage, and Temperature (PVT) variations at nanometer technologies. This paper explores a systematic analysis of various leakage power reduction techniques at the circuit level, such as Power Gating (PG), Drain Gating (DG), LECTOR and GALEOR, and analyzes the effect of PVT variations on the dissipation and delay of leakage power using the ISCAS C17 benchmark circuit.

A Physics-Based Single Event Transient Pulse Width Model for CMOS VLSI Circuits

The single-event transients in MOSFETs due to heavy ion strikes introduce soft errors in sub-50 $nm$ CMOS VLSI circuits. These transients are easily captured and propagated in high-frequency CMOS VLSI circuits. The capture rate mainly depends on the single-event transient (SET) pulse width and the clock frequency of the circuits. An estimation of the SET pulse width through a physics-based model that considers the device electrostatics is necessary to predict and mitigate these soft errors in VLSI circuits. In this article, a physics-based bias-dependent model is developed to determine the SET pulse width of a double-gate (DG) CMOS inverter with the heavy-ion strike on OFF state NMOS. The output voltage perturbations due to ion strike in the CMOS inverter and the SET pulse width model are derived from the bias-dependent SET current model previously reported. The variations in the output voltage of the inverter and the pulse width obtained from the developed model for different Linear Energy Transfer (LET), supply bias, strike positions, device dimensions, and load capacitances are validated with TCAD mixed-mode simulations.

Transmission Gate and Hybrid Cmos Full Adder Characterization and Power-Delay Product Estimation Based on Mathematical Model

Abstract The demand for low power CMOS VLSI circuit design is increasing due to the ever-increasing demand for portable devices. A Full Adder (FA) is the basic building block of many VLSI subsystems, and it affects the performance of VLSI subsystems. The Transmission Gate (TG) and hybrid CMOS FA designs can achieve low Power Delay Product (PDP) compared to other FA designs, hence these FA designs are suitable for portable devices. A large number of repetitive simulations are required for thorough characterization of the FA design. A method to develop the mathematical model (based on 2nd degree polynomial equation) of the FA is proposed here, which satisfactorily estimates the Power Delay Product (PDP) of TG and hybrid CMOS FAs for non-simulated parameter combinations within given parameter range. Main aim of proposed method is to reduce characterization effort by estimating PDP using mathematical model, rather than estimating it through simulation. Also, mathematical model can be used to estimate the transistor widths to achieve low PDP for particular operating condition. Further, the effect of individual polynomial term, number of parameters, and number of points per parameter, on the accuracy of mathematical model is also studied.

Sleepy CMOS-Sleepy Stack (SC-SS): A Novel High Speed, Area and Power Efficient Technique for VLSI Circuit Design

This paper presents a novel ultra-low-power Sleepy CMOS-Sleepy Stack (SC-SS) technique for nano scale VLSI technologies. Eight prior techniques are taken for comparison with proposed technique on 65[Formula: see text]nm technology. All the techniques are applied on four benchmark circuits: XOR gate, 1-bit adder, 1-bit comparator and 4-bit up-down counter for measurement of area consumption and total power dissipation. The proposed SC-SS technique achieved very high power efficiency as compared to Complementary CMOS technique (CCT), Dual sleep Technique (DST), Forced stack technique (FST), Sleepy keeper technique (SKT), Sleepy pass gate technique (SPGT), Sleep transistor technique (STT) and VLSI CMOS Circuit Leakage Reduction technique (VCLEARIT). Although Sleepy stack technique (SST) is power efficient as compared to SC-SS technique, this is on the expense of area and delay penalty. Proposed technique has shown the area improvement of 33% for XOR, 10.78 % for 1-bit adder, 14.9% for 1-bit comparator and 9.7% for 4-bit up-down counter over SST technique on 65[Formula: see text]nm technology. At the same time, power-area product of SC-SS is 29.56% and 54.96% less as compared to SST for XOR and 4-bit up-down counter. To obtain the efficiency of proposed technique over SST in terms of delay and power-delay product, basic inverter design is taken into consideration. Delay of SC-SS inverter is 34.8% and power-delay product is 6.9% less as compared to SST inverter on 65[Formula: see text]nm technology.

Towards an automated design flow for memristor based VLSI circuits

As today's CMOS technology is gradually scaling down to its physical limits, emerging technologies are under research as alternatives in the future, such as carbon nanotube, magnetic tunneling junction, memristor. Among them, memristor is a promising candidate to implement the futuristic VLSI circuits. It provides a great scalability, near-zero standby power consumption, etc. In order to design memristor based VLSI circuits and explore their potential, it is crucial to develop an automated design flow. However, such a design flow is still missing so far. This paper proposes an automated design flow, Mosys by reusing parts of existing CMOS VLSI circuit design tools. Mosys provides a circuit design flow from a Verilog programming interface to performance estimation models. In addition, it employs a probabilistic power estimation model instead of one based on exhaustive-searching method. In our experiments, it significantly reduces the running time up to over 3000 times with a marginal error (<1%), as compared to the state-of-the-art. To verify the whole Mosys flow, several integer arithmetic functional units (e.g., add, multiply) are described in Verilog and implemented. In addition, Mosys is compared with the state-of-the-art using the EPFL benchmark suite. The results show that Mosys significantly improves the area (6.29x) and delay (4.68x) on average.

Designing energy-efficient imprecise adders with multi-bit approximation

Since early 2000s, achieving significant energy-efficiency for CMOS VLSI circuit design has become more difficult. Approximate computing is a hopeful solution for enhancing power-efficiency in error-tolerant applications. In such systems, adders play an essential role and mainly contribute to the system's total power and area consumption. Many proposals have been introduced in the literature that build large adders while using novel low power full adder structure as its building blocks. However, single-bit structure approximation, only limits the design space of approximate adders. And leads to a poor trade-off between accuracy and power dissipation. This paper proposes a novel approach for design of multi-bit adders, based on three novel approximate 2-bit adder circuits. Simulation results demonstrates that the proposed adders consume less area and power than the state-of-the-art approximate adders. Up to 80% power improvements are attainable for the proposed designs as compared with the baseline adders.

Estimation of Delay to Consider Leakage in CMOS VLSI Circuit

In digital CMOS circuits, parametric yield improvement may be achieved by reducing the variability of performance and power consumption of individual cell instances. In recent years, increasing demand of portable digital systems has led to rapid and innovative development in the field of low power design. Such improvement of variation robustness can be attained by evaluating parameter variation impact at gate level. Statistical characterization of logic gates are usually obtained by computationally expensive electrical simulations. An efficient gate delay variability estimation method is proposed for variability-aware design. As the technology scaled down to deep nanometer level, the power supply, threshold (Vt) and device geometry gets reduces. The sub threshold current continue to increase exponentially, when the Vt of the device is reduced. The leakage current is now a dominant part of total power dissipation as the technology scales down. The proposed method has been applied to different topologies (transistor network arrangements) and CMOS gates, and it has been compared to Monte Carlo simulations for data validation, resulting in computation time savings.

Low power domino logic circuits in deep-submicron technology using CMOS

Leakage power and propagation delay are the two major challenges in designing CMOS VLSI circuits, in deep sub-micron technology. This paper proposes a novel technique: Foot Driven Stack Transistor Domino Logic (FDSTDL) for designing CMOS domino logic gates for the reduction in leakage power and improved noise performance. Two, four, eight and sixteen input OR gates are designed using existing and proposed techniques. These logic gates are simulated on the PTM 32 nm node using HSPICE (Level = 54) in CMOS technology at a clock frequency of 100 MHz. Simulation results are compared based on power consumption, propagation delay and unity noise gain. Simulation results show that proposed domino technique has a maximum power reduction of 59.47% as compared to the CSK-DL technique and maximum delay reduction of 44.6% as compared to the M-HSCD technique in CMOS technology.

Dynamic Power Reduction in Digital VLSI Circuits Using Stacked LCNMOS

In deep submicron technologies, leakage power becomes a key for a low power design due to its ever increasing proportion in chips total power consumption. Power dissipation is an important consideration in the design of CMOS VLSI circuits. High power consumption leads to reduction in battery life in case of battery powered applications and affects reliability packaging and cooling costs. We propose a technique called Stacked LCNMOS for designing CMOS gates. LCNMOS technique significantly cuts down the leakage current without increasing switching power dissipation. LCNMOS, a technique to tackle the leakage problem in all digital circuits, uses single additional Leakage Control Transistor (LCT) driven by the output from the pull up and pull down networks, which is placed in a path from pull down network to ground. This LCT provides the additional resistance thereby reducing leakage current in path from supply to ground. In stacked LCNMOS technique, every transistor in the network is duplicated with both the transistors bearing half the original transistor width. It overcomes the limitation of sleep technique by retaining states. All the performances has been investigated using 90nm technology at one voltage and evaluated by the comparison of the simulation result obtained from T-SPICE

A Review on Various Leakage Power Reduction Techniques in Deep Submicron Technologies in CMOS VLSI Circuits

A Review on Various Leakage Power Reduction Techniques in Deep Submicron Technologies in CMOS VLSI Circuits

An improved low transition test pattern generator for low power applications

VLSI circuits are perceived to dissipate extra power during testing when compared with that of the normal function. Drastic heat may reduce circuit consistency, shoot up package cost, and even cause permanent damage to the circuit under test. Thus minimization of test power has gained increased significance. This paper explores the avenues in power minimization during test application in CMOS VLSI circuits since power consumption during testing is high when compared to normal operation. Design of low transition Test Pattern Generators is one usual method adopted to reduce power consumption. In the Proposed Modified Low Transition Linear Feedback Shift Register, power dissipation during testing is reduced by minimizing the switching activity between successive test vectors by comparing the two consecutive test vectors and inserting random bit such that total number of transitions is reduced without affecting the randomness. Significant advantage of this method is reduced power consumption with reduced complexity when compared to other existing methods. Considering experimental results there is a significant reduction in power consumption up to 36.2% for ISCAS'85 combinational bench mark circuits and up to 10% for ISCAS'89 Benchmark sequential circuit with marginal increase in area overhead.